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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 50/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
50
218us, a controlled slip will occur. The contents of a single frame of DS1 data will be skipped or repeated, this
will cause the following events to occur:
The status register bit TSLP will toggle (see Table 112 - T1 Transmit Elastic Buffer Status - R Address
Y14).
The latched status register bit TSLPL = 1 (see Table 136 - T1 Elastic Store Status Latch - R Address
Y26).
The interrupt status register bit TSLPI = 1 (see Table 153 - T1 Elastic Store Interrupt Status - R Address
Y36), if unmasked with mask control register bit TSLPM = 0 (see Table 160 - T1 Elastic Store Interrupt
Mask - R/W Address Y46).
The direction of the slip is indicated with status register bit TSLPD (see Table 112 - T1 Transmit Elastic Buffer
Status - R Address Y14). The relative phase delay between the system frame boundary and the transmit
elastic frame read boundary is measured every second frame and reported in the status register bits
TXSBMSB, TXTS4-0 and TXBC2-0 (see Table 112 - T1 Transmit Elastic Buffer Status - R Address Y14). In
addition the relative offset between these frame boundaries may be programmed by writing to control register
bits TXSD7-0 (see Table 184 - T1 Transmit Elastic Buffer Set Delay - R/W Address YF7. Every write to this
register resets the transmit elastic frame count status register bit TXSBMSB. After a write, the delay through
the slip buffer is less than 1 frame in duration. Each write operation will result in a disturbance of the transmit
DS1 frame boundary, causing the far end to go out of sync.
Writing BC (hex) into register bits TXSD7-0 maximizes the wander tolerance before a controlled slip occurs.
Under normal operation no slips should occur in the transmit path. Slips will only occur if the input CKb clock
has excess wander, or the register bits TXSD7-0 are initialized to close to the slip pointers after system
initialization.
6.1.2
T1 Receive Slip Buffer
The two frame receive elastic buffer is attached between the 1.544 Mb/s DS1 receive side and the 2.048 Mb/s
ST-BUS side of the MT9071. Besides performing rate conversion, this elastic buffer is configured as a slip
buffer which absorbs wander and low frequency jitter in multi-trunk applications. The received DS1 data is
clocked into the slip buffer with the RxCK clock and is clocked out of the slip buffer with the system CKb clock.
The RxCK extracted clock is generated from, and is therefore phase-locked with, the receive DS1 data.
In the case of Line Sync Mode (see Table 1 - E1 and T1 Timing Modes Summary), the CKb clock is phase
locked to one of the four extracted RxCK clocks by an internal phase locked loop (PLL).
single trunk, the receive data is in phase with the RxCK clock, the CKb clock is phase locked to the RxCK
clock, and the read and write positions of the slip buffer track each other.
Therefore for this
In a multi-trunk slave or loop-timed system (i.e., PABX application) a single trunk will be chosen as a network
synchronizer, which will function as described in the previous paragraph. The remaining trunks will use the
system timing derived from the synchronizer to clock data out of their slip buffers. Even though the DS1 signals
from the network are synchronous to each other, due to multiplexing, transmission impairments and route
diversity, these signals may jitter or wander with respect to the synchronizing trunk signal. Therefore, the RxCK
clocks of non-synchronized trunks may wander with respect to the RxCK clock of the synchronizer and the
system bus. Network standards state that, within limits, trunk interfaces must be able to receive error-free data
in the presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The
MT9071 will allow 92us (140 UI, DS1 unit intervals) of wander and low frequency jitter before a frame slip will
occur.
When the CKb and the RxCK clocks are not phase-locked, the rate at which data is being written into the slip
buffer from the DS1 side may differ from the rate at which it is being read out onto the ST-BUS. If this situation
persists, the delay limits stated in the previous paragraph will be violated and the slip buffer will perform a
controlled frame slip. That is, the buffer pointers will be automatically adjusted so that a full DS1 frame is either
repeated or lost. All frame slips occur on frame boundaries.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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