
MT9071
Preliminary Information
68
11.2.2
Data Link Pin Data (RxD) Received from PCM30 - With No Elastic Buffer
The RxD signal is aligned with the receive extracted clock RxCK. The HDB3 decoded receive data, at 2.048Mb/
s, is clocked out of the device on the RxD pin with the rising edge of RxCK. No DL data will be lost or repeated
when a receive frame slip occurs as the DL data does not pass through the elastic buffer. In order to facilitate
the attachment of this data stream to a Data Link controller, the RxBF pin outputs a frame boundary indicating
the start of timeslot 0 containing the Sa bits.
11.2.3
E1 Data Link ST-BUS Access
When the ST-BUS data link access is enabled, the setting of the ST-BUS DSTi data bits determine the data link
output on the PCM30 link corresponding to bit positions four to eight (Sa4-8) over each Non-Frame Alignment
Signal (NFAS) frame. Data for data link transmission should be written to DSTi immediately following the NFAS
frame (during FAS frames) and before the start of the next NFAS frame.
Similarly, the data link data received on the PCM30 link is output to ST-BUS DSTo timeslot 0 during NFAS
frames. However, the data link data on ST-BUS DSTo timeslot 0 of NFAS frames is always enabled, regardless
the control register bit settings.
Table 25 - E1 National Bits mapping to ST-BUS DST shows the detailed bit mapping of DSTi timeslots to
transmit PCM30 timeslots.
11.2.4
E1 Data Link HDLC Access
The Data Link can be connected to the internal HDLC, operating at a bit rate of 4/8/12/16 or 20 kbits/s,
depending on the number of Sa bits enabled for transmission/reception on the HDLC with the SA control
register bits detailed in Table 95 - E1 Data Link Control - R/W Address Y08.
Addressable Bytes
NFAS Frames of a CRC-4 Multiframe
Transmit
Address
Receive
Address
F1
B7
F3
B6
F5
B5
F7
B4
F9
B3
F11
B2
F13
B1
F15
B0
TN0
TN1
TN2
TN3
TN4
YB0
YB1
YB2
YB3
YB4
RN0
RN1
RN2
RN3
RN4
YC0
YC1
YC2
YC3
YC4
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
S
a4
S
a5
S
a6
S
a7
S
a8
Table 24 - E1 National Bit Buffers
ST-BUS DSTi/DSTo
PCM30 Transmit/Receive
CRC-4
Frame
Timeslot
Data Bits (B7-B0)
Timeslot
CRC-4
Frame
Data Bits (B1-B8)
All NFAS
0 for 2Mb/s
0,1,2,3 for
8Mb/s
Sa8, Sa7, Sa6, Sa5, Sa4, P3,
P2, P1
0
All NFAS
P1, P2, P3, Sa4, Sa5, Sa6,
Sa7, Sa8
Note 1. P1-3 are not transmitted from DSTi but are received on DSTo.
Table 25 - E1 National Bits mapping to ST-BUS DST