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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 39/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
39
4.1.2
Status register bit PDV (see Table 104 - T1 Synchronization and Alarm Status - R Address Y10) toggles if the
receive data fails to meet ones density requirements. It will toggle upon detection of 16 consecutive zeros on
the line data, or if there are fewer than N ones in a window of 8(N+1) bits - where N = 1 to 23.
T1 Pulse Density
If control register bit TPDV (see Table 80 - T1 Line Coding Control - R/W Address Y01) is set, then the output
T1 data to be sent is monitored and if the 12.5% density requirement is detected over a maximum 192 bit
window a one is inserted in a non-framing and non-signaling bit. The window and PDV criteria is the same as
the received PDV. If this option is disabled the transmit data is sent unaltered.
4.2
T1 Frame Alignment
In T1 mode, the MT9071 will synchronize to DS1 lines formatted with either the D4 or ESF protocol. In either
mode the framer maintains a running 3 bit history of received data for each of the candidate bit positions.
Candidate bit positions whose incoming patterns fail to match the predicted pattern (based on the 3 bit history)
are winnowed out. If, after a 10 bit history has been examined, only one candidate bit position remains within
the framing bit period, the receive side timebase is forced to align to that bit position. If no candidates remain
after a 10 bit history, the process is re-initiated. If multiple candidates exist after a 24 bit history time-out period,
the framer forces the receive side timebase to synchronize to the next incoming valid candidate bit position. In
the event of a reframe, the framer starts searching at the next bit position over. This prevents persistent locking
to a mimic as the controller may initiate a software controlled reframe in the event of locking to a mimic.
Under software control the framing criteria may be tuned with control register bit CXC (see Table 78 - T1
Framing Mode Control - R/W Address Y00).
Selecting D4 framing invites a further decision whether or not to include a cross check of Fs bits along with the
Ft bits. If Fs bits are checked (set CXC control register bit high), multiframe alignment is forced at the same
time as terminal frame alignment. If only Ft bits are checked, multiframe alignment is forced separately, upon
detection of the Fs bit history of 00111 (for normal D4 trunks). For D4 trunks, a reframe on the multiframe
alignment may be forced at any time without affecting terminal frame alignment.
In ESF mode the circuit will optionally confirm the CRC-6 bits before forcing a new frame alignment. This is
programmed by setting control register bit CXC high. A CRC-6 confirmation adds a minimum of 6 milliseconds
to the reframe time. If no CRC-6 match is found after 16 attempts, the framer moves to the next valid candidate
bit position (assuming other bit positions contain a match to the framing pattern) or re-initiates the whole
framing procedure (assuming no bit positions have been found to match the framing pattern).
The framing circuit is off - line. During a reframe, the rest of the circuit operates synchronous with the last frame
alignment. Until such time as a new frame alignment is achieved, the signaling bits are frozen in their states at
the time that frame alignment was lost, and error counting for Ft, Fs, ESF framing pattern or CRC-6 bits is
suspended.
4.3
T1 Reframe
The MT9071 will automatically force a reframe if the framing bit error density exceeds the threshold
programmed with control register bits RS1-0 (see Table 78 - T1 Framing Mode Control - R/W Address Y00).
RS1 = RS0 = 0 forces a reframe for 2 errors out of a sliding window of 4 framing bits. RS1 = 0, RS0 = 1 forces
a reframe with 2 errors out of 5. RS1 = 1, RS0 = 0 forces a reframe with 2 errors out of 6. RS1 = RS0 = 1
disables the automatic reframe.
In ESF mode all framing bits are checked.
In D4 mode, bit checking selection is done with control register bit FSI (see Table 78 - T1 Framing Mode
Control - R/W Address Y00). If FSI is set low, only Ft bits are checked. If FSI is set high, both Ft and Fs bits are
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