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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 183/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
183
9
RXDO
(0)
TXMFE
(0)
SPND
(0)
Receive DSTo All Ones.
If one, the DSTo pin operates normally. If zero, all timeslots (0-31) of
DSTo are set to one.
Transmit Multiframe Enable.
If one, the TxMF pin will be enabled. If zero, the TxMF pin will be
disabled. See the TxMF pin description.
Suspend Interrupts.
If zero, the selected tranceivers contribution to the IRQ pin output will be
a high impedance state, but all interrupt and latched status registers will continue to be
updated. If one, the selected tranceivers contribution to the IRQ output will be normal
operation.
Interrupt Acknowledge.
If zero, all interrupt and latched status registers are cleared and
consequently, the selected tranceivers contribution to the IRQ pin output will be a high
impedance state. If one, all interrupt and latched status registers operate normally, and the
selected tranceivers contribution to the IRQ output will be normal operation.
Output DSTo Enable.
If one, the DSTo pin operates normally. If zero, DSTo will be at high
impedance.
CSTo Enable.
If one, the CSTo pin operates normally. If zero, CSTo will be at high impedance.
8
7
6
INTA
(0)
5
DSTOE
(0)
CSTOE
(0)
RXCO
(0)
CNCLR
(0)
ACCLR
(0)
4
3
Receive CSTO All Ones
.If one, the CSTo pin operates normally. If zero, all timeslots of CSTo
are set to one
Counter Clear.
When this bit is changed from zero to one, status counters are cleared. If zero,
all status counters operate normally.
Automatic Counter Clear.
When this bit is set to one, all latchable status counters are cleared
automatically by the one second timer bit ONESEC (Table 106 - T1 Timer Status - R Address
Y11) immediately following the counter latch operation. If zero, all latchable status counters
operate normally.
Reset
. When this bit is changed from zero to one, the selected framer (Y) will reset to its
default mode. See Section 7.6 Reset Operation (RESET, TRST Pins).
Table 178 - T1 Interrupt and I/O Control - R/W Address YF1
2
5
0
RST
(0)
Bit
Name
Functional Description
15-11
10
(#### #)
ADREC
(0)
Not Used
Address Recognition Enable.
When high, address recognition is enabled. This forces the
receiver to recognize only those packets having the unique address as programmed in the T1
& E1 HDLC Address Recognition Control - R/W Address YF4, or if the address is an all call
address providing control bit A2EN of the same register is set high. When ADREC is low, all
received packets are stored in the Receive FIFO.
Receiver Enable.
When high, the HDLC receiver will be immediately enabled. When low, the
HDLC receiver is disabled. If a packet is received when this bit goes low, the receiver will
disable after the packet is finished.
Transmitter Enable.
When high, the transmitter will be immediately enabled and will begin
transmitting data, if any, or go to a mark idle or interframe time fill state. When low, the HDLC
transmitter is disabled. If a packet is transmitted when this bit goes low, the transmitter will
disable after the packet is finished.
End of Packet.
When high, the next byte written to the Transmit FIFO is aborted and an EOP
byte is sent to the transmitter instead, and following this byte, an FCS is transmitted. This
facilitates loading of multiple packets into the Transmit FIFO. This bit is reset automatically
after a write to the Transmit FIFO. See Section 12.0 HDLC.
Frame Abort
. When high, the next byte written to the Transmit FIFO is tagged. After the write,
the FA bit is cleared. When the tagged byte reaches the bottom of the FIFO, an abort
sequence is sent instead of the tagged byte, see Section 12.1.4 Frame Abort.
Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2
9
RXEN
(0)
8
TXEN
(0)
7
EOP
(0)
6
FA
(0)
Bit
Name
Functional Description
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| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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