- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384760 > MT9071 (Mitel Networks Corporation) Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）) PDF資料下載
參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 147/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁當(dāng)前第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁
Preliminary Information
MT9071
147
7
6
5
4
3
2
1
0
RXF7
RXF6
RXF5
RXF4
RXF3
RXF2
RXF1
RXF0
HDLC Receive FIFO Data.
This is the received data byte read from the Receive FIFO. The
FIFO status is not changed immediately when a receiver write or processor read occurs. It is
updated after the data has settled and the transfer to the last available position has finished.
Bit
Name
Functional Description
15-9
8
(0000 000)
GAL
(0)
Not Used
Go Ahead Latch.
When the HDLC receiver detects a go-ahead pattern (01111111), this
status bit is latched to one. This bit is cleared when either this register, or the T1 & E1 HDLC
Interrupt Status - R Address Y33 is read.
End of Packet Detect Latch.
When the HDLC receiver writes an end of packet (EOP) byte
into the Receive FIFO, this status bit is latched to one. This can be in the form of a flag
(01111110), an abort sequence (x1111111x) or as an invalid packet. This bit is cleared when
either this register, or the T1 & E1 HDLC Interrupt Status - R Address Y33 is read.
Transmit End of Packet Latch.
When the HDLC transmitter has finished sending the
closing flag of a packet or after a packet has been aborted, this status bit is latched to one.
This bit is cleared when either this register, or the T1 & E1 HDLC Interrupt Status - R Address
Y33 is read.
End of Packet Read Latch.
When there is only one byte of data left in the Receive FIFO,
and this data is the last byte of the packet, this status bit is latched to one. It is also set if the
Receive FIFO is read and there is no data in it. This bit is cleared when either this register, or
the T1 & E1 HDLC Interrupt Status - R Address Y33 is read.
Transmit FIFO Low Latch.
When the HDLC transmitter empties the Transmit FIFO below
16 bytes, this status bit is latched to one. This bit is cleared when either this register, or the
T1 & E1 HDLC Interrupt Status - R Address Y33 is read.
Frame Abort Latch.
When the HDLC receiver detects an abort sequence (x1111111x), this
status bit is latched to one. Note that it must be received after a minimum number of bits have
been received (26), otherwise it is ignored. This bit is cleared when either this register, or the
T1 & E1 HDLC Interrupt Status - R Address Y33 is read.
Transmit FIFO Empty Latch.
When the HDLC transmitter reads an empty Transmit FIFO,
this status bit is latched to one. This bit is cleared when either this register, or the T1 & E1
HDLC Interrupt Status - R Address Y33 is read.
Receive FIFO High Latch.
When the Receive FIFO is filled above 16 bytes, this status bit is
latched to one. This bit is cleared when either this register, or the T1 & E1 HDLC Interrupt
Status - R Address Y33 is read.
Receive FIFO Overflow Latch.
When the HDLC receiver writes to an already full Receive
FIFO, this status bit is latched to one. This bit is cleared when either this register, or the T1 &
E1 HDLC Interrupt Status - R Address Y33 is read. The HDLC will disable the receiver once
the receive overflow has been detected. The receiver will be re-enabled upon detection of the
next flag, but will overflow again unless the Receive FIFO is read.
Table 131 - T1 & E1 HDLC Latched Status - R Address Y23
7
EOPDL
(0)
6
TEOPL
(0)
5
EOPRL
(0)
4
TXFLL
(0)
3
FAL
(0)
2
TXFEL
(0)
1
RXFHL
(0)
0
RXFOL
(0)
Bit
Name
Functional Description
Table 130 - T1 & E1 HDLC Receive FIFO Data - R/W Address Y1F
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級通道開關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。