
Preliminary Information
MT9071
23
20.1 T1 & E1 Global Transceiver Registers Bit Summary - Address 900-914...............................................92
20.2 T1 & E1 Unique HDLC Registers Bit Summary - Address Y1C-Y1F, Y23, Y33, Y43, YF2-YF6............93
20.3 T1 & E1 Unique LIU Registers Bit Summary - Address YE0-YE4 .........................................................94
20.4 T1 Unique Framer Registers Bit Summary - Address Y00- YF7............................................................95
20.5 E1 Unique Framer Registers Bit Summary - Address Y00 - YC4 ........................................................100
21.0 T1 & E1 Transceiver Registers Bit Functions...........................................................106
21.1 T1 & E1 Global Transceiver Register Bit Functions - in Address Order...............................................106
21.2 T1 & E1 Unique Transceiver Register Bit Functions - in Address Order..............................................114
22.0 MT9071 and Network Specifications..........................................................................186
22.1 T1 Intrinsic Jitter...................................................................................................................................186
22.2 T1 Jitter Tolerance ...............................................................................................................................186
22.3 Jitter Transfer .......................................................................................................................................187
22.4 E1 Intrinsic Jitter...................................................................................................................................187
22.5 E1 Jitter Tolerance ...............................................................................................................................187
22.6 E1 Jitter Transfer..................................................................................................................................188
23.0 Applications.................................................................................................................189
23.1 Master Clock ........................................................................................................................................189
23.1.1 Clock Oscillator
23.1.2 Crystal Oscillator
23.2 4 Trunk T1, E1 or J1 Cross-Connect with LDX and Synchronous Backplane .....................................191
23.3 8 Trunk T1, E1 or J1 Interface with LDX, Remote Timing, Internal PLL and Synchronous Backplane191
23.4 8 T1, E1 or J1 Links with MT90220 Octal IMA/UNI and Synchronous Backplane...............................192
23.5 4 T1,E1 or J1 Links with Synchronous Common Channel Signaling ...................................................193
23.6 8 Trunk T1, E1 or J1 Interface with LDX, CCS and 8.192Mb/s Synchronous Backplane....................194
23.7 Interfacing the 3.3V MT9071 with 5V Logic Levels ..............................................................................195
23.8 T1 & E1 Analog Line Interface .............................................................................................................196
23.9 256 Pin LBGA to 128 Pin LQFP Mapping and 4 Layer PCB Layout....................................................200
189
190
24.0 AC and DC Electrical Characteristics........................................................................201