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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 70/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
70
HDLC does not distinguish between the control and information fields and a packet does not need to contain an
information field to be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CRC-CCITT standard generator polynomial “X
16
+X
12
+X
5
+1” produces the 16-bit FCS. In the transmitter the
FCS is calculated on all bits of the address and data field. The complement of the FCS is transmitted, most
significant bit first, in the FCS field. The receiver calculates the FCS on the incoming packet address, data and
FCS field and compares the result to “F0B8”. If no transmission errors are detected and the packet between the
flags is at least 32 bits in length then the address and data are entered into the receive FIFO minus the FCS
which is discarded.
12.1.2
Data Transparency (Zero Insertion/Deletion)
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of 5 contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
12.1.3
Invalid Frames
A frame is invalid if one of the following four conditions exists (Inserted zeros are not part of a valid count):
If the FCS pattern generated from the received data does not match the “F0B8” pattern, then the last
data byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the
receiver and nothing is written to the receive FIFO.
Packets which are at least 25 bits in length but less than 32 bits between the flags are also invalid. In
this case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.
If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside
in the receive FIFO, assuming the packet length before the abort sequence was at least 26 bits long.
12.1.4
Frame Abort
The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of the
normal packet. The receiver will abort upon reception of seven contiguous 1s occurring between the flags of a
packet which contains at least 26 bits.
Note that should the last received byte before the frame abort end with contiguous 1s, these are included in the
seven 1s required for a receiver abort. This means that the location of the abort sequence in the receiver may
occur before the location of the abort sequence in the originally transmitted packet. If this happens then the last
data written to the receive FIFO will not correspond exactly with the last byte sent before the frame abort.
12.1.5
Interframe Time Fill and Link Channel States
When the HDLC transmitter is not sending packets it will wait in one of two states.
Interframe Time Fill state: This is a continuous series of flags occurring between frames indicating that
the channel is active but that no data is being sent.
Idle state: An idle Channel occurs when at least 15 contiguous 1s are transmitted or received.
In both states the transmitter will exit the wait state when data is loaded into the transmitter FIFO.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級(jí)通道開關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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