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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 71/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
71
12.1.6
Go-Ahead
A go ahead is defined as the pattern “011111110” (contiguous 7Fs) and is the occurrence of a frame abort
sequence followed by a zero, outside of the boundaries of a normal packet. Being able to distinguish a proper
(in packet) frame abort sequence from one occurring outside of a packet allows a higher level of signaling
protocol which is not part of the HDLC specifications.
12.2 HDLC Functional Description
The HDLC transceiver can be reset by either the power reset input signal or by the HRST control register bit
detailed in Table 180 - T1 & E1 HDLC Control 1 - R/W Address YF3. When reset, the HDLC control registers
(see Table 48 - T1 & E1 HDLC Control Registers - Address YF2-YF6) are cleared, resulting in the transmitter
and receiver being disabled. The Receiver and Transmitter can be enabled independent of one another through
control register bits RXEN and TXEN detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2.
Transmit to receive loopback as well as a receive to transmit loopback are also supported with control register
bits RTLOOP and HLOOP detailed in Table 180 - T1 & E1 HDLC Control 1 - R/W Address YF3.
Received packets from the serial interface are sectioned into bytes by the HDLC receiver that detects flags,
checks for go-ahead signals, removes inserted zeros, performs a cyclical redundancy check (CRC) on
incoming data, and monitors the address if required. Packet reception begins upon detection of an opening
flag. The resulting bytes are concatenated with status register bits RQ9 and RQ8 (see Table 128 - T1 & E1
HDLC Status - R/W Address Y1D), and placed in the receiver first-in-first-out (RX FIFO); a buffer register that
generates status and interrupts for microprocessor read control.
In conjunction with the control circuitry, the microprocessor writes data bytes into a transmit buffer register (TX
FIFO) that generates status and interrupts. Packet transmission begins when the microprocessor writes a byte
to the TX FIFO. Two status register bits are added to the TX FIFO for transmitter control of frame aborts (FA)
and end of packet (EOP) flags. Packets have flags appended, zeros inserted, and a CRC, also referred to as
frame checking sequence (FCS), added automatically during serial transmission. When the TX FIFO is empty
and finished sending a packet, Interframe Time Fill bytes (continuous flags (7E hex)), or Mark Idle (continuous
ones) are transmitted to indicate that the channel is idle.
12.2.1
HDLC Transmitter
Following initialization and enabling, the transmitter is in the Idle Channel state (Mark Idle), continuously
sending ones. Interframe Time Fill state (Flag Idle) is selected by setting the mark idle bit MI detailed in Table
179 - T1 & E1 HDLC Control 0 - R/W Address YF2 high. The Transmitter remains in either of these two states
until data is written to the TX FIFO. Control register bits EOP (end of packet) and FA (Frame Abort) detailed in
Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2 are set as status bits before the microprocessor loads
8 bits of data into the 10 bit wide FIFO (8 bits data and 2 bits status). To change the tag bits being loaded in the
FIFO, the control register must be written to before writing to the FIFO. However, EOP and FA are reset after
writing to the TX FIFO. The counter detailed in Table 183 - T1 & E1 HDLC Transmit Packet Size - R/W Address
YF6 may also be used to tag an end of packet. The register is loaded with the number of bytes in the packet
and decrements after every write to the TX FIFO. When a count of one is reached, the next byte written to the
FIFO is tagged as an end of packet. The register may be made to cycle through the same count if the packets
are of the same length by setting the CYCLE bit detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address
YF2.
If the transmitter is in the Idle Channel state when data is written to the TX FIFO, then an opening flag is sent
and data from TX FIFO follows. Otherwise, data bytes are transmitted as soon as the current flag byte has
been sent. TX FIFO data bytes are continuously transmitted until either the FIFO is empty or an EOP or FA
status bit is read by the transmitter. After the last bit of the EOP byte has been transmitted, a 16-bit FCS is sent
followed by a closing flag. When multiple packets of data are loaded into TX FIFO, only one flag is sent
between packets.
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