
Preliminary Information
MT9071
175
3
RA(n)
(#)
RB(n)
(#)
RC(n)
(#)
RD(n)
(#)
Receive Channel Associated Signaling (CAS) Signaling Bits for Channel 1 to 30.
Address Y51 to Y5F correspond to n=1 to n=15 which correspond to channel 1 to 15
and the corresponding RA, RB, RC & RD bits are received from the PCM30 link in
timeslot 16 in bit positions one to four respectively, in frame n.
Address Y61 to Y6F correspond to n=17 to n=31 which correspond to channel 16 to 30
and the corresponding RA, RB, RC & RD bits are received from the PCM30 link in
timeslot 16 in bit positions five to eight respectively, in frame n-16.
2
1
0
For CAS operation, the signaling bit enable control register bit CSIG (see Table 85 - E1 DL, CCS, CAS and Other Control - R/W
Address Y03) must be set to zero.
Refer to 10.2 E1 CAS.
Table 165 - E1 Receive CAS Data Registers - R Address Y71-Y7F, Y81-Y8F
Bit
Name
Functional Description
15-10 (#### ##) Not Used
9
RPCI(n)
(0)
Receive Per Channel inversion.
If one, the data received from the incoming DS1 channel is
inverted before it emerges from the corresponding DSTo channel. If zero, this feature is
disabled.
Micro Port Data Receive.
If one, the receive idle code data register bits RXIDC7-0 (See Table
96 - T1 Receive Idle Code Data - R/W Address Y09) replace the normal DSTo channel data. If
zero, this feature is disabled.
Micro Port Signaling Transmit.
If one, the transmit CAS bits (A,B,C & D) are sourced from the
transmit CAS data register bits TAn, TBn, TCn & TDn (see Table 162 - T1 Transmit CAS Data
Registers - R/W Address Y50-Y67) instead of the CSTi channel serial data stream. If zero, this
feature is disabled.
Transmit Per Channel inversion.
If one, the data sourced from the DSTi channel is inverted
before being transmitted onto the DS1 channel. If zero, this feature is disabled.
Remote Timeslot Loopback.
If one, the data received on the RTIP/RRNG channel is looped
back to the transmit TTIP/TRNG channel. The received channel is also present on DSTo. If
zero, this feature is disabled. See Section 15.0 Loopbacks.
Local Timeslot Loopback.
If one, the data sourced from the DSTi channel is looped back to
the DSTo channel. The transmitted channel is also present on TTIP/TRNG. If zero, this feature
is disabled. See Section 15.0 Loopbacks.
Transmit Test.
If one, the mu-law digital milliwatt (if control bit ADSEQ is one, see Table 80 - T1
Line Coding Control - R/W Address Y01) or a PRBS generator (if control bit ADSEQ is zero) will
be transmitted in the corresponding DS1 channel. More than one channel may be activated at
once. If zero, this feature is disabled.
Receive Test.
If one, the mu-law digital milliwatt (if control bit ADSEQ is one, see Table 80 - T1
Line Coding Control - R/W Address Y01) or a PRBS detector (if control bit ADSEQ is zero) will
be transmitted in the corresponding DSTo channel. More than one channel may be activated at
once. If zero, this feature is disabled.
Micro Port Data Transmit.
If one, the transmit idle code data register bits TXIDC7-0 (See Table
98 - T1 Transmit Idle Code Data - R/W Address Y0A) replace the normal DS1 channel data. If
zero, this feature is disabled.
Clear Channel.
If one, no robbed bit signaling is inserted in the equivalent transmit DS1
channel. If zero, robbed bit signaling is enabled.
8
MPDR(n)
(0)
7
MPST(n)
(0)
6
TPCI(n)
(0)
RTSL(n)
(0)
5
4
LTSL(n)
(0)
3
TTST(n)
(0)
2
RRST(n)
(0)
1
MPDT(n)
(0)
0
CC(n)
(0)
Note: Address Y90-YA7 corresponds to n=1 to n=24 which corresponds to DS1 channel 1 - 24
Table 166 - T1 Per Channel 1 to 24 Control Registers - R/W Address Y90-YA7
Bit
Name
Functional Description