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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 111/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
111
5
X1RI
(0)
T1 Transceiver 1 Receive Interrupt.
When any bit in the T1 Transceiver 1 - T1 Receive Line and
Timer Interrupt Status - R Address Y35 (Y=1) is set to one, this status bit is one; otherwise, it is
zero. The corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked
for this operation to function.
T1 Transceiver 1 Sync Interrupt.
When any bit in the T1 Transceiver 1 - T1 Receive and Sync
Interrupt Status - R Address Y34 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 0 HDLC Interrupt.
When any bit in the T1 Transceiver 0 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 0 Elastic Interrupt.
When any bit in the T1 Transceiver 0 - T1 Elastic Store
Interrupt Status - R Address Y36 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 0 Receive Interrupt.
When any bit in the T1 Transceiver 0 - T1 Receive Line and
Timer Interrupt Status - R Address Y35 (Y=0) is set to one, this status bit is one; otherwise, it is
zero. The corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked
for this operation to function.
T1 Transceiver 0 Sync Interrupt.
When any bit in the T1 Transceiver 0 - T1 Receive and Sync
Interrupt Status - R Address Y34 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
Table 74 - T1 Interrupt Vector Status - R Address 910
4
X1SI
(0)
3
X0HI
(0)
2
X0EI
(0)
1
X0RI
(0)
0
X0SI
(0)
Bit
Name
Functional Description
15
X3HI
(0)
E1 Transceiver 3 HDLC Interrupt.
When any bit in the E1 Transceiver 3 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 3 National Interrupt.
When any bit in the E1 Transceiver 3 - E1 National Interrupt
Status - R Address Y36 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 3 Counter Interrupt.
When any bit in the E1 Transceiver 3 - E1 Counter Interrupt
Status - R Address Y35 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 3 Sync Interrupt.
When any bit in the E1 Transceiver 3 - E1 Sync Interrupt Status
- R Address Y34 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The corresponding
bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this operation to
function.
E1 Transceiver 2 HDLC Interrupt.
When any bit in the E1 Transceiver 2 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
Table 75 - E1 Interrupt Vector Status - R Address 910
14
X3NI
(0)
13
X3CI
(0)
12
X3SI
(0)
11
X2HI
(0)
Bit
Name
Functional Description
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