
MT9071
Preliminary Information
4
Data Link
One Embedded Floating HDLC per Framer
Flag generation and Frame Check Sequence (FCS) generation and detection, zero insertion and
deletion
Continuous flags, or continuous 1s are transmitted between frames
Transmit frame-abort
Invalid frame handling:
Frames yielding an incorrect FCS are tagged as bad packets
Frames with fewer than 25 bits are ignored
Frames with fewer than 32 bits between flags are tagged as bad packets
Frames interrupted by a Frame-Abort sequence remain in the FIFO and an interrupt is generated
Access is provided to the receive FCS
FCS generation can be inhibited for terminal adaptation
Recognizes single byte, dual byte and all call addresses
Independent, 32 byte deep transmit and receive FIFOs
Receive FIFO maskable interrupts for nearly full and overflow conditions
Transmit FIFO maskable interrupts for nearly empty and underflow conditions
Maskable interrupts for transmit end-of–packet and receive end-of-packet
Maskable interrupts for receive bad-frame (includes frame abort)
Transmit-to-receive and receive-to-transmit loopbacks are provided
Transmit and receive bit rates and enables are independent
Frame aborts can be sent under software control and they are automatically transmitted in the event of
a transmit FIFO underrun
Common Channel Signaling Timeslot Assigner
Selected 64 Kbit/s CCS channels (for V5.2 and GR-303) can be routed to/from an external multichannel
HDLC, using the CSTi/o pins
T1/J1 Mode
E1 Mode
Three methods are provided to access
the datalink:
1. RxD pin supports receive datalink
2. Bit Oriented Messages are supported via
internal registers
3. An internal HDLC can be assigned to
transmit/receive over the FDL in ESF
mode
Two methods are provided to access the datalink:
1. RxD pin supports receive datalink over the Sa4~Sa8
bits
2
.
An internal HDLC can be assigned to transmit/
receive data via the Sa4~Sa8 bits
In transparent mode, if the Sa4 bit is used for an
intermediate datalink, the CRC-4 remainder can be
updated to reflect changes to the Sa4 bit
T1/J1 Mode
E1 Mode
Assignable to the ESF Facility Data Link or
any other channel
Assignable to timeslot-0, bits Sa4~Sa8 or
any other timeslot
Operates at 4 kbit/s (FDL), 56 kbit/s or
64 kbit/s
Operates at 4, 8, 12, 16 or 20 kbit/s (Sa bits)
or 64 kbit/s