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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 153/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
153
Bit
Name
Functional Description
15-4
(0000 0000
0000)
EZOL
(0)
Not Used
3
Excessive Zero Counter Overflow Latch.
When the corresponding counter (T1 Excessive
Zero’s Counter - R/W Address Y1B) overflows to 0, this status bit is latched to one. It is
cleared when either this register, or the T1 Elastic Store Interrupt Status - R Address Y36 is
read.
Excessive Zero Counter Indication Latch.
When the corresponding counter (T1 Excessive
Zero’s Counter - R/W Address Y1B) is incremented by one, this status bit is latched to one. It
is cleared when either this register, or the T1 Elastic Store Interrupt Status - R Address Y36 is
read.
Transmit SLIP Latch.
When the TSLP status bit (T1 Transmit Elastic Buffer Status - R
Address Y14) toggles from zero to one, or from one to zero, this status bit is latched to one. It
is cleared when either this register, or the T1 Elastic Store Interrupt Status - R Address Y36 is
read.
Receive SLIP Latch.
When the RSLP status bit (T1 Receive Elastic Buffer Status - R
Address Y13) toggles from zero to one, or from one to zero, this status bit is latched to one. It
is cleared when either this register, or the T1 Elastic Store Interrupt Status - R Address Y36 is
read.
Table 136 - T1 Elastic Store Status Latch - R Address Y26
2
EZIL
(0)
1
TSLPL
(0)
0
RSLPL
(0)
Bit
Name
Functional Description
15
14
(0)
Not Used
Sa5 Bit Value Latch.
This is the latched value of the Sa5 National bit when the Sa6N8L bit (of
this register) toggles to one. It is cleared when either this register, or the E1 National Interrupt
Status - R Address Y36 is read.
Sa6 Nibble (bit 3 to 0) Value Latch.
This is the latched value of the Sa6 National bits nibble
(bits 3 to 0) when the Sa6N8L bit (of this register) toggles to one. They are cleared when
either this register, or the E1 National Interrupt Status - R Address Y36 is read.
Sa5VL
13
12
11
10
9
Sa6V3L
Sa6V2L
Sa6V1L
Sa6V0L
Sa6N8L
Sa6 Nibble Eight Consecutive Times Status Latch.
When eight consecutive identical
receive Sa6 National bit nibble patterns are received (per sub-multiframe), this status bit is
latched to one. This bit is set on a CRC-4 sub-multiframe basis. It is cleared when either this
register, or the E1 National Interrupt Status - R Address Y36 is read.
Sa6 Nibble Change Status Latch.
When a received Sa6 National bit nibble (per sub-
multiframe) changes value, this status bit is latched to one. This bit is set on a CRC-4 sub-
multiframe basis. This bit is cleared when either this register, or the corresponding interrupt
status register (register address Y36) is read.
Sa Nibble Change Status Latch.
When any receive National (i.e. Sa5,Sa6,Sa7 or Sa8) bits
nibbles changes value, this status bit is latched to one. This bit is set on a CRC-4 sub-
multiframe basis. It is cleared when either this register, or the E1 National Interrupt Status - R
Address Y36 is read.
Sa5 Bit Change Status Latch.
When a received Sa5 National bit changes value, this status
bit is latched to one. This bit is set on a CRC-4 NFAS frame basis. It is cleared when either this
register, or the E1 National Interrupt Status - R Address Y36 is read.
Sa Bit Change Status Latch.
When any receive National (i.e. Sa5,Sa6,Sa7 or Sa8) bit
changes value, this status bit is latched to one. This bit is set on a CRC-4 NFAS frame basis.
It is cleared when either this register, or the E1 National Interrupt Status - R Address Y36 is
read.
Table 137 - E1 National Latched Status - R Address Y26
8
Sa6NL
7
SaNL
6
Sa5TL
5
SaTL
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