
MT9071
Preliminary Information
82
17.2 E1 Error Insertion
Six types of error conditions can be inserted into the transmit PCM 30 data stream through control register bits,
which are detailed in Table 81 - E1 Test, Error and Loopback Control - R/W Address Y01. These error events
include the bipolar violation errors (BVE), CRC-4 errors (CRCE), FAS errors (FASE), NFAS errors (NFSE),
payload (PERR) and a loss of signal error (LOSE). The LOSE function overrides the HDB3 encoding function
(no BPV are added). Also included are E1 and E2 error bit insertion on frames 13 and 15.
17.3 E1 Per Timeslot Control
There are 32 per timeslot control registers occupying a total of 32 unique addresses (see Table 167 - E1 Per
Timeslot 0 to 31 Control Registers - R/W Address Y90-YAF). Each register controls a matching timeslot on the
32 transmit channels (onto the line) and the equivalent channel data on the receive (DSTo) data. For example,
register address Y90 of the first per timeslot control register contains program control for transmit timeslot 0
and DSTo channel 0.
Counter
Counter 1 Sec. Latch
Counter Indication
Counter Overflow
Latch
Int.
Mask Latch
Int.
Mask
Table 115 - E1 PRBS Error
Counter & PRBS CRC
Multiframe Counter - R/W
Address Y15
PEC7-0
PCC7-0
Table 117 - E1 Loss of Basic
Frame Sync Counter - R/W
Address Y16
SLC15-0
Table 119 - E1 E-bit Error
Counter - R/W Address Y17
EEC15-0
Table 121 - E1 Bipolar Violation
Error Counter - R/W Address
Y18
VEC15-0
Table 123 - E1 CRC-4 Error
Counter - R/W Address Y19
CEC15-0
Table 125 - E1 FAS Bit Error
Counter & FAS Error Counter -
R/W Address Y1A
BEC7-0
FEC7-0
Y25 - See Table 135 - E1 Counter Latched Status - R Address Y25
Y35 - See Table 152 - E1 Counter Interrupt Status - R Address Y35
Y45 - See Table 159 - E1 Counter Interrupt Mask - R/W Address Y45
NA
Y25
NA
Y35
NA
Y45
NA
Y25
Y25
Y35
Y35
Y45
Y45
PEIL
NA
PEII
NA
PEIM
NA
PEOL
PCOL
Y24
PEOI
PCOI
Y34
PEOM
PCOM
Y44
NA
NA
SLOL SLOI
Y25
SLOM
Y45
Table 140 - E1 E-Bit Error Count
Latch - R Address Y28
EEL15-0
Table 142 - E1 Bipolar Violation
Error Count Latch - R/W Address
Y29
VEL15-0
Table 144 - E1 CRC-4 Error
Count Latch - R/W Address Y2A
CEL15-0
Table 146 - E1 FAS Error Count
Latch - R/W Address Y2B
Y25
Y35
Y45
Y35
EEIL
Y25
EEII
Y35
EEIM EEOL EEOI EEOM
Y45
Y25
Y35
Y45
VEIL
Y25
VEII
Y35
VEIM VEOL VEOI VEOM
Y45
Y25
Y35
Y45
CEIL
Y25
Y25
CEII
Y35
Y35
CEIM CEOL CEOI CEOM
Y45
Y45
Y25
Y25
Y35
Y35
Y45
Y45
BEL7-0
FEL7-0
BEIL
FEIL
BEII
FEII
BEIM
FEIM
BEOL
FEOL
BEOI
FEOI
BEOM
FEOM
Table 34 - E1 Error Counters Summary