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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 163/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
163
Bit
Name
Functional Description
15
D4YI
(0)
D4 Yellow Interrupt.
This bit is one when the corresponding D4YL bit in the T1 Receive Line
Status and Timer Latch - R Address Y25 is set, and the corresponding D4YM bit in the T1 Receive
Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
D4 Y48 Interrupt.
This bit is one when the corresponding D4Y48L bit in the T1 Receive Line
Status and Timer Latch - R Address Y25 is set, and the corresponding D4Y48M bit in the T1
Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Secondary Yellow Interrupt.
This bit is one when the corresponding SECYL bit in the T1
Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding SECYM bit in
the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
ESF Yellow Interrupt.
This bit is one when the corresponding ESFYL bit in the T1 Receive Line
Status and Timer Latch - R Address Y25 is set, and the corresponding ESFYM bit in the T1
Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
T1DM Yellow Interrupt.
This bit is one when the corresponding T1DMYL bit in the T1 Receive
Line Status and Timer Latch - R Address Y25 is set, and the corresponding T1DMYM bit in the T1
Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Not Used
Bipolar Violation Counter Indication Interrupt.
This bit is one when the corresponding VEIL bit
in the T1 Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding
VEIM bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This
bit is cleared when either this register, or the latched status register is read.
PRBS Error Counter Indication Interrupt.
This bit is one when the corresponding PEIL bit in the
T1 Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding PEIM bit
in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Pulse Density Violation Interrupt.
This bit is one when the corresponding PDVL bit in the T1
Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding PDVM bit in
the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Line Loop Code Enable Detected Interrupt.
This bit is one when the corresponding LLEDL bit in
the T1 Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding
LLEDM bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Line Loop Code Disable Detected Interrupt.
This bit is one when the corresponding LLDDL bit
in the T1 Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding
LLDDM bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Bit Oriented Message Interrupt.
This bit is one when the corresponding BOML bit in the T1
Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding BOMM bit in
the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Bit Oriented Message Match Interrupt.
This bit is one when the corresponding BOMML bit in
the T1 Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding
BOMMM bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Table 151 - T1 Receive Line and Timer Interrupt Status - R Address Y35
14
D4Y48I
(0)
13
SECYI
(0)
12
ESFYI
(0)
11
T1DMYI
(0)
10
9
(0)
VEII
(0)
8
PEII
(0)
7
PDVI
(0)
6
LLEDI
(0)
5
LLDDI
(0)
4
BOMI
(0)
3
BOMMI
(0)
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