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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 167/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
167
Bit
Name
Functional Description
15-9
8
(#### ###)
GAM
(0)
Not Used
Go Ahead Mask.
This is the mask bit for the corresponding GAI bit in the T1 & E1 HDLC
Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will remain inactive.
If this mask bit is zero, the interrupt bit will function normally.
End of Packet Detect Mask.
This is the mask bit for the corresponding EOPDI bit in the T1
& E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Transmit End of Packet Mask.
This is the mask bit for the corresponding TEOPI bit in the
T1 & E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
End of Packet Read Mask.
This is the mask bit for the corresponding EOPRI bit in the T1 &
E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Transmit FIFO Low Mask.
This is the mask bit for the corresponding TXFLI bit in the T1 &
E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Frame Abort Mask.
This is the mask bit for the corresponding FAI bit in the T1 & E1 HDLC
Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will remain inactive.
If this mask bit is zero, the interrupt bit will function normally.
Transmit FIFO Empty Mask.
This is the mask bit for the corresponding TXUNDERI bit in the
T1 & E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Receive FIFO High Mask.
This is the mask bit for the corresponding RXFFI bit in the T1 &
E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Receive FIFO Overflow Mask.
This is the mask bit for the corresponding RXOVFLI bit in the
T1 & E1 HDLC Interrupt Status - R Address Y33. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Table 155 - T1 & E1 HDLC Interrupt Mask - R/W Address Y43
7
EOPDM
(0)
6
TEOPM
(0)
5
EOPRM
(0)
4
TXFLM
(0)
3
FAM
(0)
2
TXFEM
(0)
1
RXFHM
(0)
0
RXFOM
(0)
Bit
Name
Functional Description
15
BEOM
(0)
Framing Bit Error Counter Overflow Mask.
This is the mask bit for the corresponding BEOI
bit in the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
CRC-6 Error Counter Overflow Mask.
This is the mask bit for the corresponding CEOI bit in
the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Out Of Frame Counter Overflow Mask
. This is the mask bit for the corresponding OFOI bit in
the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Change of Frame Alignment Counter Overflow Mask.
This is the mask bit for the
corresponding CFOI bit in the T1 Receive and Sync Interrupt Status - R Address Y34. If this
mask bit is one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will
function normally.
Bipolar Violation Counter Overflow Mask.
This is the mask bit for the corresponding VEOI
bit in the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Table 156 - T1 Receive and Sync Interrupt Mask - R/W Address Y44
14
CEOM
(0)
13
OFOM
(0)
12
CFOM
(0)
11
VEOM
(0)
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