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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 73/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
73
The RQ8 and RQ9 status register bits detailed in Table 128 - T1 & E1 HDLC Status - R/W Address Y1D, are
appended to each data byte as it is written to the RX FIFO. They indicate that a good packet has been received
(good FCS and no frame abort), or a bad packet with either incorrect FCS or frame abort. The status and
interrupt registers (see Table 148- T1 & E1 HDLC Interrupt Status - R Address Y33) should be read before
reading the RX FIFO since status and interrupt information correspond to the byte at the output of the FIFO
(i.e. the byte about to be read). The status register bits are encoded as follows:
RQ9
1
0
1
0
RQ8
1
1
0
0
Byte status
last byte (bad packet)
first byte
last byte (good packet)
packet byte
The end-of-packet-detect interrupt bit EOPDI (see Table 148 - T1 & E1 HDLC Interrupt Status - R Address Y33)
indicates that the last byte written to the RX FIFO was an EOP byte (last byte in a packet). The end-of-packet-
read (EOPRI) interrupt indicates that the byte about to be read from the RX FIFO is an EOP byte (last byte in a
packet). The status register should be read to see if the packet is good or bad before the byte is read.
A minimum size packet has an 8-bit address, an 8-bit control byte, and a 16-bit FCS pattern between the
opening and closing flags (see Section 12.1.1 HDLC Frame Structure). Thus, the absence of a data
transmission error and a frame length of at least 32 bits results in the receiver writing a valid packet code with
the EOP byte into RX FIFO. The last 16 bits before the closing flag are regarded as the FCS pattern and will
not be transferred to the receiver FIFO. Only data bytes (Address, Control, Information) are loaded into the RX
FIFO.
In the case of an RX FIFO overflow, no clocking occurs until a new opening flag is received. In other words, the
remainder of the packet is not clocked into the FIFO. Also, the top byte of the FIFO will not be written over. If
the FIFO is read before the reception of the next packet then reception of that packet will occur. If two
beginning of packet conditions (RQ9=0;RQ8=1) are seen in the FIFO, without an intermediate EOP status,
then overflow occurred for the first packet.
The receiver may be enabled independently of the transmitter. This is done by setting the RXEN bit detailed in
Table 179- T1 & E1 HDLC Control 0 - R/W Address YF2. Enabling happens immediately upon writing to the
register. Disabling using RXEN will occur after the present packet has been completely loaded into the FIFO.
Disabling can occur during a packet if no bytes have been written to the FIFO yet. Disabling will consist of
disabling the internal receive clock. The FIFO, Status, and Interrupt Registers may still be read while the
receiver is disabled. Note that the receiver requires a flag before processing a frame, thus if the receiver is
enabled in the middle of an incoming packet it will ignore that packet and wait for the next complete one.
The receive CRC can be monitored with the CRC15-0 status bits detailed in Table 129 - T1 & E1 HDLC
Receive CRC Data - R/W Address Y1E. This register contains the actual CRC sent by the other transmitter in
its original form; that is, MSB first and bits inverted. This register is updated by each end of packet (closing flag)
received and therefore should be read when an end of packet is received so that the next packet does not
overwrite the register.
13.0 Transparent Mode Operation
Both T1 and E1 modes provide a transparent mode of operation where framing is not imposed in the transmit
direction.
13.1 T1 Transparent Mode Operation
Setting control register bit TRANSP (see Table 78 - T1 Framing Mode Control - R/W Address Y00) enables
transparent mode operation which causes unframed data to be transmitted from DSTi channels 0 to 23 and
channel 31 bit 7 onto the DS1 line. Unframed data received from the DS1 line is piped out on DSTo channels 0
to 23 and channel 31 bit 0.
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