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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 149/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
149
3
SEFL
(0)
Severely Errored Frame Latch.
When the SEF status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive and Sync Interrupt Status - R Address
Y34 is read.
AIS Latch.
When the AIS status bit (T1 Synchronization and Alarm Status - R Address Y10)
toggles from zero to one, this status bit is latched to one. It is cleared when either this
register, or the T1 Receive and Sync Interrupt Status - R Address Y34 is read.
CRC-6 Error Counter Indication Latch
. When the corresponding counter (T1 CRC-6 Error
Counter - R/W Address Y19) is incremented by one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive and Sync Interrupt Status - R Address Y34
is read.
Digital Loss of Signal Latch.
When the LOS status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive and Sync Interrupt Status - R Address
Y34 is read.
Table 132 - T1 Receive Sync and Alarm Latch - R Address Y24
2
AISL
(0)
1
CEIL
(0)
0
LOSL
(0)
Bit
Name
Functional Description
15
14
(0)
Not Used
RCRCRL
Remote CRC-4 and RAI Latch.
When the RCRCR status bit (E1 Synchronization & CRC-
4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to
one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34
is read.
RSLPL
Receive Slip Latch.
When the RSLP status bit (E1 Synchronization & CRC-4 Remote Status
- R Address Y10) toggles from zero to one, or from one to zero, this status bit is latched to one.
It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is read.
YL
Receive Y-bit Latch.
When the Y status bit (E1 Alarms & MAS Status - R Address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. It is cleared
when either this register, or the E1 Sync Interrupt Status - R Address Y34 is read.
AUXPL
Auxiliary Pattern Latch.
When the AUXP status bit (E1 Alarms & MAS Status - R Address
Y12) toggles from zero to one, this status bit is latched to one. It is cleared when either this
register, or the E1 Sync Interrupt Status - R Address Y34 is read.
RAIL
Remote Alarm Indication Status Latch.
When the RAI (A) status bit (E1 Alarms & MAS
Status - R Address Y12) toggles from zero to one, or from one to zero, this status bit is latched
to one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34
is read.
AISL
Alarm Indication Status Signal Latch.
When the AIS status bit (E1 Alarms & MAS Status - R
Address Y12) toggles from zero to one, or from one to zero, this status bit is latched to one. It
is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is read.
AIS16L
Alarm Indication Signal 16 Status Latch.
When the AIS16 status bit (E1 Alarms & MAS
Status - R Address Y12) toggles from zero to one, or from one to zero, this status bit is latched
to one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34
is read.
LOSSL
Loss of Signal Status Indication Latch.
When the LOSS status bit (E1 Alarms & MAS
Status - R Address Y12) toggles from zero to one, or from one to zero, this status bit is latched
to one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34
is read.
Table 133 - E1 Sync Latched Status - R Address Y24
13
12
11
10
9
8
7
Bit
Name
Functional Description
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