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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 110/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
110
1
ESYNI
(0)
ESYN Input Enable.
When zero, the bi-directional ESYN pin is an input. When one, the bi-
directional ESYN pin is an output. Set this in accordance with the timing mode detailed in Section
3.0 Timing.
Fast Lock.
When one, the PLL is underdamped and it acquires lock faster than normal. This is
typically used in conjunction with the PSLP control bit detailed in
T1 & E1 Global Mode Control - R/W Address 900. When zero, the PLL behaves normally.
Table 73 - T1 & E1 Global Timing Control - R/W Address 905
0
FLOCK
(0)
Bit
Name
Functional Description
15
X3HI
(0)
T1 Transceiver 3 HDLC Interrupt.
When any bit in the T1 Transceiver 3 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 3 Elastic Interrupt.
When any bit in the T1 Transceiver 3 - T1 Elastic Store
Interrupt Status - R Address Y36 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 3 Receive Interrupt.
When any bit in the T1 Transceiver 3 - T1 Receive Line and
Timer Interrupt Status - R Address Y35 (Y=3) is set to one, this status bit is one; otherwise, it is
zero. The corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked
for this operation to function.
T1 Transceiver 3 Sync Interrupt.
When any bit in the T1 Transceiver 3 - T1 Receive and Sync
Interrupt Status - R Address Y34 (Y=3) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 2 HDLC Interrupt.
When any bit in the T1 Transceiver 2 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 2 Elastic Interrupt.
When any bit in the T1 Transceiver 2 - T1 Elastic Store
Interrupt Status - R Address Y36 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 2 Receive Interrupt.
When any bit in the T1 Transceiver 2 - T1 Receive Line and
Timer Interrupt Status - R Address Y35 (Y=2) is set to one, this status bit is one; otherwise, it is
zero. The corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked
for this operation to function.
T1 Transceiver 2 Sync Interrupt.
When any bit in the T1 Transceiver 2 - T1 Receive and Sync
Interrupt Status - R Address Y34 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 1 HDLC Interrupt.
When any bit in the T1 Transceiver 1 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
T1 Transceiver 1 Elastic Interrupt.
When any bit in the T1 Transceiver 1 - T1 Elastic Store
Interrupt Status - R Address Y36 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the T1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
Table 74 - T1 Interrupt Vector Status - R Address 910
14
X3EI
(0)
13
X3RI
(0)
12
X3SI
(0)
11
X2HI
(0)
10
X2EI
(0)
9
X2RI
(0)
8
X2SI
(0)
7
X1HI
(0)
6
X1EI
(0)
Bit
Name
Functional Description
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