
Preliminary Information
MT9071
77
15.1 T1 Mode In Band Loopback Codes
T1.403 defines SF mode line loopback activate and deactivate codes. These codes are either a framed or
unframed repeating bit sequence of 00001 for activation or 001 for deactivation. The standard goes on to say
that these codes will persist for five seconds or more before the loopback action is taken. The MT9071 will
detect both framed and unframed line activate and de-activate codes even in the presence of a BER of 3 x 10
-
3
. Status register bit LLDD (see Table 104 - T1 Synchronization and Alarm Status - R Address Y10) will be
asserted when a repeating 001 pattern (either framed or unframed) has persisted for 48 milliseconds. Status
register bit LLED (see Table 104 - T1 Synchronization and Alarm Status - R Address Y10) will be asserted
when a repeating 00001 pattern (either framed or unframed) has persisted for 48 milliseconds.
Other loopup and down codes can be selected by writing to the transmit loop up and loop down code registers
(see Table 101 - T1 Transmit Loop Activate Code Control - R/W Address Y0D and Table 102 - T1 Transmit Loop
Deactivate Code Control - R/W Address Y0E).
The selection of the expected received loopup and loopdown code is done by writing to the receive loop up and
loop down code match registers (see Table 103 - T1 Receive Loop Activate Code Match Control - R/W Address
Y0F and Table 177 - T1 Receive Loop Deactivate Code Match - R/W Address YF0).
Maskable interrupt status bits LLEDI and LLDDI will be set upon detection of inband loopup or loopdown codes
respectively (see Table 149 - T1 Receive and Sync Interrupt Status - R Address Y34 and Table 156 - T1
Receive and Sync Interrupt Mask - R/W Address Y44).
16.0 T1 Maintenance and Alarms
16.1 T1 Error Counters
The MT9071 has nine T1 error counters for each framer, which can be used for maintenance testing, for
ongoing measure of the quality of a DS1 link and to assist the designer in meeting specifications such as
TR62411 and T1.403. All counters can be preset or cleared by writing to the appropriate locations. In addition,
all counters may be cleared by programming the counter clear bit CNCLR (see Table 178 - T1 Interrupt and I/O
Control - R/W Address YF1) low to high. Associated with each counter is a maskable event occurrence
interrupt and a maskable counter overflow interrupt. Overflow interrupts are useful when cumulative error
counts are being recorded. Associated with four counters are the 1 second latched registers. These registers
are updated with their corresponding counter values on a one second interval. Counters can automatically be
cleared after their data is latched by setting control register bit ACCLR (see Table 178 - T1 Interrupt and I/O
Control - R/W Address YF1) high.
For a full listing of all available T1 counters, latches, interrupts and masks, refer to Table 31 - T1 Error Counters
Summary.
TTIP-TRNG
DSTo
DS1 or PCM30
System
RTIP-RRNG
Framer