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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 72/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
72
Frame aborts (the transmission of 7F hex), are transmitted by tagging a byte previously written to the TX FIFO.
When a byte has an FA tag, then an FA is sent instead of that tagged byte. That is, all bytes previous to but not
including that byte are sent. After a Frame Abort, the transmitter returns to the Mark Idle or Interframe Time Fill
state, depending on the state of the Mark idle control register bit.
TX FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun occurs.
Below is an example of the transmission of a three byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill).
(a) Set MI bit - Write ’04’ hex to the register detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2
(b) Load 1st data byte - Write ’AA’ hex to the register detailed in Table 182 - T1 & E1 HDLC Transmit FIFO Data
- R/W Address YF5
(c) Load 2nd data byte - Write ’03’ hex to the register detailed in Table 182 - T1 & E1 HDLC Transmit FIFO Data
- R/W Address YF5
(d) Set MI, TXEN, EOP bits - Write ’34’ hex to the register detailed in Table 179 - T1 & E1 HDLC Control 0 - R/
W Address YF2
(e) Load final data byte - Write ’77’ hex to the register detailed in Table 182 - T1 & E1 HDLC Transmit FIFO
Data - R/W Address YF5
The transmitter may be enabled independently of the receiver. This is done by setting the TXEN bit of the
control register detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2.
Enabling happens immediately upon writing to the register. Disabling using TXEN will occur after the
completion of the transmission of the present packet; the contents of the FIFO are not cleared. Disabling will
consist of stopping the transmitter clock. The Status and Interrupt Registers may still be read and the FIFO and
Control Registers may be written to while the transmitter is disabled. The transmitted FCS may be inhibited
using the TCRCI bit detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2. In this mode the
opening flag followed by the data and closing flag is sent and zero insertion still included, but no CRC. That is,
the FCS is injected by the microprocessor as part of the data field. This is used in V.120 terminal adaptation for
synchronous protocol sensitive UI frames.
12.2.2
HDLC Receiver
After initialization and enabling, the receiver clocks in serial data, continuously checking for Go-aheads (0 1111
1110), flags (0111 1110), and Idle Channel states (at least fifteen ones). When a flag is detected, the receiver
synchronizes itself to the serial stream of data bits, automatically calculating the FCS. If the data length
between flags after zero removal is less than 25 bits, then the packet is ignored so no bytes are loaded into RX
FIFO. When the data length after zero removal is between 25 and 31 bits, a first byte and bad FCS code are
loaded into the RX FIFO (see definition of RQ8 and RQ9 below). For an error-free packet, the result in the CRC
register should match the HEX pattern of ’F0B8’ when a closing flag is detected.
If address recognition is required, the receiver address recognition register (see Table 181 - T1 & E1 HDLC
Address Recognition Control - R/W Address YF4) is loaded with the desired address and the ADREC bit
detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2 is set high. Control register bits A2EN and
A1EN are used as an enable bit for the two bytes, thus allowing either or both of the first two bytes to be
compared to the expected values. Bit 0 of the first byte of the address received (address extension bit) will be
monitored to determine if a single or dual byte address is being received. If this bit is 0 then a two byte address
is being received and then only the first six bits of the first address byte are compared. An all call condition is
also monitored for the second address byte; and if received the first address byte is ignored (not compared with
mask byte). If the address extension bit is a 1 then a single byte address is being received. In this case, an all
call condition is monitored for in the first byte as well as the mask byte written to the comparison register and
the second byte is ignored. Seven bits of address comparison can be realized on the first byte if this is a single
byte address by setting control register bit SEVEN detailed in Table 179 - T1 & E1 HDLC Control 0 - R/W
Address YF2.
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PDF描述 |
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| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT90710 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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| MT9072AB | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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