- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384760 > MT9071 (Mitel Networks Corporation) Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 83/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)當(dāng)前第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)
Preliminary Information
MT9071
83
17.3.1
E1 Per Timeslot Trunk Conditioning
The received data on a DSTo timeslot can be replaced by the idle code data bits RXIDC7-0 detailed in Table 97
- E1 Receive Idle Code Data - R/W Address Y09 on a per channel basis when programmed with control
register bit MPDR in the per channel control registers detailed in Table 167 - E1 Per Timeslot 0 to 31 Control
Registers - R/W Address Y90-YAF.
Similarly, the transmitted data from a DSTi timeslot can be replaced by the idle code data bits TXIDC7-0
detailed in Table 99 - E1 Transmit Idle Code Data - R/W Address Y0A on a per channel basis when
programmed with control register bit MPDT in the per channel control registers detailed in Table 167 - E1 Per
Timeslot 0 to 31 Control Registers - R/W Address Y90-YAF.
The received data on a DSto timeslot can also be inverted on a per channel basis by setting control bit RPCI
detailed in Table 167 - E1 Per Timeslot 0 to 31 Control Registers - R/W Address Y90-YAF.
Similarly, the transmitted data from a DSTi timeslot can also be inverted on a per channel basis by setting
control bit TPCI detailed in Table 167 - E1 Per Timeslot 0 to 31 Control Registers - R/W Address Y90-YAF.
17.3.2
See Section 15.0 Loopbacks.
E1 Per Timeslot Looping
17.3.3
E1 Per Timeslot PRBS Testing
The MT9071 includes both a pseudo random bit sequence (PRBS) generator of type (2
15
-1), and a reverse
PRBS generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted
PRBS type (2
15
-1). Bits which don’t match are counted by an internal error counter. This provides for powerful
system debugging and testing without additional external hardware.
If control register bit ADSEQ (see Table 81 - E1 Test, Error and Loopback Control - R/W Address Y01) is zero,
any transmit (internal DSTi) timeslot or combination of transmit timeslots may be connected to the PRBS
generator. Timeslot n is selected by setting the TTSTn bit detailed in Table 167 - E1 Per Timeslot 0 to 31
Control Registers - R/W Address Y90-YAF, where n is 0 to 31. Any data sent on DSTi is overwritten on the
selected timeslots before being output to TTIP/TRNG.
Similarly, if control register bit ADSEQ is zero, any receive timeslot or combination of receive timeslots may be
connected to the PRBS decoder. Timeslot n is selected by setting the RRSTn bit detailed in Table 167 - E1 Per
Timeslot 0 to 31 Control Registers - R/W Address Y90-YAF, where n is 0 to 31. Data on DSTo is not affected.
PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data
received must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the
data.
If one channel is tested at a time, then the PRBS transmit timeslot does not have to match the PRBS receive
timeslot. However, if more than one channel is tested, then the number of transmit timeslots must match the
number of receive timeslots, and the order of the transmit timeslots must match the order of the receive
timeslots. This will ensure that the sequential data bytes received by the PRBS decoder are in the correct
order. Consequently, particular care must be taken when using an external loopback where the channel order
may be reversed, or where the data has passed through a digital switch which doesn’t buffer all channels to the
same degree.
The PRBS decoder must have sufficient data pass through it before it begins to operate correctly, therefore, the
errors generated by the decoder immediately following start-up should be ignored.
If the PRBS testing is performed in an external loop around using timeslot control, then both timeslot control
register bits TTSTn and RRSTn should be set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開(kāi)關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開(kāi)關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開(kāi)關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級(jí)通道開(kāi)關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。