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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 86/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
86
multiframe alarm (Y-bit) signal to the far end of the link. This transmission will cease when signaling multiframe
alignment is acquired.
18.0 T1 & E1 Interrupts
The MT9071 has an extensive suite of interrupts consisting of one maskable interrupt vector and 16 maskable
interrupt status registers. See Figure 15 - T1 & E1 Interrupt Registers Overview. The set bits in the interrupt vector
identify which of the 16 interrupt status registers are responsible for the interrupt. Reading the corresponding
interrupt status registers identifies the exact source of the interrupt. Any set bit in the interrupt vector causes the
IRQ pin to toggle low, providing the SPND bit is not enabled (see Section 18.1.1 T1 & E1 Interrupt Related
Control Bits and Pins).
18.1 T1 & E1 Interrupt Status Register Overview
All 16 interrupt status registers are maskable with 16 corresponding interrupt mask registers. All interrupt status
registers and all interrupt mask registers are 16 bit, although all 16 bits are not always used. Unused status register
bits are zero if read.
When an unmasked interrupt occurs, one or more bits of the 16 interrupt status registers will go high causing one
or more bits of the unmasked interrupt vector to go high. A high bit in the interrupt vector causes the output IRQ pin
to go low. After an interrupt status register is read, it is automatically cleared. After all interrupt status registers are
cleared, the interrupt vector is cleared causing the IRQ pin to return to a high impedance state.
If a new unmasked interrupt occurs while the interrupt status registers from a previous interrupt are being read,
the affected interrupt status registers will be updated, the interrupt vector will be updated, and the IRQ pin will
remain low until the interrupt vector is cleared (which occurs when all interrupt status registers are cleared).
If the interrupt status registers are unmasked, and the interrupt vector is masked, then the interrupt status
registers will function normally but the interrupt vector status register will remain low and the IRQ pin will be in a
high impedance state.
18.1.1
T1 & E1 Interrupt Related Control Bits and Pins
SPND
- All interrupts for a particular transceiver may be suspended without changing the interrupt mask words,
by setting the SPND control register bit to zero. For T1 mode see Table 178 - T1 Interrupt and I/O Control - R/
W Address YF1. For E1 mode see Table 83 - E1 Interrupts and I/O Control - R/W Address Y02. All unmasked
interrupt status registers will continue to be updated (and will be cleared when read), and the interrupt vector
status register will continue to reflect the status of the interrupt status register bits. However, the transceivers
with the SPND bits set to zero will not toggle the IRQ pin. If all four transceivers SPND bits are zero, then none
of the transceivers can toggle the IRQ pin.
INTA
- All interrupt status registers for a particular transceiver may be cleared (without reading the interrupt
status registers) by setting the INTA control register bit to zero. For T1 mode see Table 178 - T1 Interrupt and I/
O Control - R/W Address YF1. For E1 mode see Table 83 - E1 Interrupts and I/O Control - R/W Address Y02.
Interrupt status registers for a particular transceiver will be cleared (and not updated) as long as INTA is low.
Consequently, the selected transceivers interrupt vector bits will remain at zero, therefore that transceiver will
not toggle the IRQ pin.
TAIS
- During initial power up, all (4 transceivers) interrupt status registers are cleared without changing the
interrupt mask words, when the TAIS control pin is held low. Consequently, the interrupt vector will remain clear
and the IRQ pin will remain in a high impedance state. This allows for system initialization without spurious
interrupts. Interrupt status registers will not be updated, and the IRQ pin will be forced to a high impedance state
as long as TAIS is low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開(kāi)關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開(kāi)關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開(kāi)關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級(jí)通道開(kāi)關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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