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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 145/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
145
Bit
Name
Functional Description
15-8 (#### ####) Not Used
7
6
5
4
3
2
1
0
EZC0
(0000 0000)
EZC7
EZC6
EZC5
EZC4
EZC3
EZC2
EZC1
Excessive Zero Counter.
These bits make up a counter which is incremented for each
detection of 8 or more zeros if B8ZS (see Table 80 - T1 Line Coding Control - R/W Address
Y01) is turned on; or for each detection of 16 or more zeros if B8ZS is turned off. In other
words, this counter counts groups of 8 or more or 16 or more zeros separated by ones.
Table 126 - T1 Excessive Zero’s Counter - R/W Address Y1B
Bit
Name
Functional Description
15-12 (####) Not Used.
11
RXCLK
Receive Clock.
This bit represents the receiver clock generated after the RXEN bit detailed in
Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2, but before zero deletion is considered.
10
TXCLK
Transmit Clock.
This bit represents the transmit clock generated after the TXEN bit detailed in
Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2, but before zero insertion is considered.
9
VCRC
Valid CRC
. This is the CRC recognition status bit for the HDLC receiver. Data is clocked into the
data register detailed in Table 129 - T1 & E1 HDLC Receive CRC Data - R/W Address Y1E. If the
comparison was successful, then this bit will be high.
8
VADDR
Valid Address.
This is the address recognition status bit for the HDLC receiver. Data is clocked
into the device and compared with the data register detailed in Table 181 - T1 & E1 HDLC
Address Recognition Control - R/W Address YF4. If the comparison was successful, then this bit
will be high.
7
6
5
4
3
2
1
0
TBP0
automatically sends the two byte FCS and then the 1 byte closing FLAG. If the CYCLE bit of the
T1 & E1 HDLC Control 0 - R/W Address YF2 is set high, the counter will cycle through the
programmed value continuously.
Table 127 - T1 & E1 HDLC Test and Transmit Byte Status - R/W Address Y1C
TBP7
TBP6
TBP5
TBP4
TBP3
TBP2
TBP1
Transmit Byte Counter Position.
These 8 bits provide the position of the next byte of data to be
written into the Transmit FIFO (see Table 182 - T1 & E1 HDLC Transmit FIFO Data - R/W Address
YF5). The initial transmit byte counter position is loaded from control register bits TPS7-0 detailed
in Table 183 - T1 & E1 HDLC Transmit Packet Size - R/W Address YF6.
The transmitter automatically decrements this register following each write to the Transmit FIFO.
When this register reaches the count of one, the next write to the Transmit FIFO will be
automatically tagged as an EOP byte. Consequently, following the last byte, the transmitter
Bit
Name
Functional Description
15-7 (#### #### #) Not Used
6
IDC
Idle Channel State.
This bit is set to one when an idle channel state (15 or more ones) has
been detected at the receiver. This is an asynchronous event. On power reset, this may be
one, status becomes valid after the first zero or first15 bits are received.
Table 128 - T1 & E1 HDLC Status - R/W Address Y1D
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| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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