
Preliminary Information
MT9071
165
6
VEII
(0)
Bipolar Violation Error Counter Indication Interrupt.
This bit is one when the corresponding
VEIL bit in the E1 Counter Latched Status - R Address Y25 is set, and the corresponding VEIM
bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
E-Bit Error Counter Overflow Interrupt.
This bit is one when the corresponding EEOL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding EEOM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
E-Bit Error Counter Indication Interrupt.
This bit is one when the corresponding EEIL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding EEIM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
PRBS CRC-4 Counter Overflow Interrupt.
This bit is one when the corresponding PCOL bit
in the E1 Counter Latched Status - R Address Y25 is set, and the corresponding PCOM bit in
the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Jitter Attenuator Interrupt.
This bit is one when the corresponding JAL bit in the E1 Counter
Latched Status - R Address Y25 is set, and the corresponding JAM bit in the E1 Counter
Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
PRBS Error Counter Overflow Interrupt.
This bit is one when the corresponding PEOL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding PEOM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
PRBS Error Counter Indication Interrupt.
This bit is one when the corresponding PEIL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding PEIM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Table 152 - E1 Counter Interrupt Status - R Address Y35
5
EEOI
(0)
4
EEII
(0)
3
PCOI
(0)
2
JAI
(0)
1
PEOI
(0)
0
PEII
(0)
Bit
Name
Functional Description
15-4
3
(#### ##)
EZOI
(0)
Not Used
Excessive Zero Counter Overflow Interrupt.
This bit is one when the corresponding
EZOL bit in the T1 Elastic Store Status Latch - R Address Y26 is set, and the corresponding
EZOM bit in the T1 Elastic Store Interrupt Mask - R/W Address Y46 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Excessive Zero Counter Indication Interrupt.
This bit is one when the corresponding
EZIL bit in the T1 Elastic Store Status Latch - R Address Y26 is set, and the corresponding
EZIM bit in the T1 Elastic Store Interrupt Mask - R/W Address Y46 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Transmit SLIP Interrupt.
This bit is one when the corresponding TSLPL bit in the T1
Elastic Store Status Latch - R Address Y26 is set, and the corresponding TSLPM bit in the
T1 Elastic Store Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Receive SLIP Interrupt.
This bit is one when the corresponding RSLPL bit in the T1 Elastic
Store Status Latch - R Address Y26 is set, and the corresponding RSLPM bit in the T1
Elastic Store Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Table 153 - T1 Elastic Store Interrupt Status - R Address Y36
2
EZII(0)
1
TSLPI
(0)
0
RSLPI
(0)
Bit
Name
Functional Description