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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 14/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
14
E2
E1
F2
F1
11
12
15
16
CSTo[0]
CSTo[1]
CSTo[2]
CSTo[3]
Control ST-BUS (CMOS compatible output).
In 2.048Mb/s backplane mode,
this output delivers a 2.048Mb/s serial stream which contains up to 32 8-bit
timeslots. In T1/J1 mode, 24 of these timeslots map to the T1 link CAS ABCD bits.
In E1 mode, selected timeslots map to either the E1 link CAS bits or the E1 link
CCS bits.
In 8.192Mb/s backplane mode, CSTo[0] outputs a single 8.192Mb/s serial stream
which contains 128 8-bit timeslots accommodating all four tranceivers. CSTo[1:3]
are high impedance.
See Figure 39 - ST-BUS 2.048Mb/s Timing and Figure 41 - ST-BUS 8.192Mb/s
Timing.
Receive Data Outputs Before Buffering
T5
T11
A13
B6
47
58
109
120
RxD[0]
RxD[1]
RxD[2]
RxD[3]
Receive Data (CMOS compatible output).
Provides a serial output stream which
contains all timeslots of the received data after decoding. This data does not pass
through the elastic buffer and is clocked out with the falling edge of RxCK. In T1
and J1 mode, the data rate is 1.544Mb/s and the decoding is B8ZS. In E1 mode,
the data rate is 2.048Mb/s and the decoding is HDB3. See Figure 49 - Receive
Data (Slip Buffer Bypass) Timing.
Receive Clock (CMOS compatible output).
This output clock is extracted from
the receive signal at the RTIP and RRNG inputs and is used internally to clock in
the receive data. In T1 and J1 modes, the clock rate is 1.544MHz. In E1 mode, the
clock rate is 2.048MHz. See Figure 50 - Receive Data (Slip Buffer Bypass)
Functional Timing.
Receive Basic Frame Pulse (CMOS compatible output).
Provides an 8kHz
basic frame pulse which is synchronized to the received data (RxD) after
decoding. This frame pulse does not pass through the elastic buffer and is clocked
out with the falling edge of RxCK. See Figure 49 - Receive Data (Slip Buffer
Bypass) Timing.
R6
R11
A12
A7
48
59
110
121
RxCK[0]
RxCK[1]
RxCK[2]
RxCK[3]
T6
T12
B11
A6
49
60
111
122
RxBF[0]
RxBF[1]
RxBF[2]
RxBF[3]
Control and Timing
R1
36
TxMF
Transmit Multiframe Boundary (CMOS compatible input).
This input is
applicable in E1 mode only. The frame pulse applied to this pin sets the
transmitted CAS multiframe boundary or the transmitted CRC-4 multiframe
boundary. The falling edge of this frame pulse identifies basic frame 0 (the start of
bit cell 7 of timeslot 0) on the ST-BUS data stream (DSTi) of the 16 frame
multiframe. The device will generate its own multiframe boundary if this pin is held
high, and is pulled high in most applications. This input is common for all four
transceivers, and is enabled on a per transceiver basis with control register bit
MFBE detailed in Table 83 - E1 Interrupts and I/O Control - R/W Address Y02.
Operation is identical in 2.048Mb/s and 8.192Mb/s modes. See Figure 43 -
Transmit Multiframe (CRC-4 or CAS) Timing.
Transmit Alarm Indication Signal (CMOS compatible input).
When zero, all
four transceivers of the MT9071 transmit an all ones signal (AIS) at the TTIP and
TRNG output pins. When one, all four transceivers of the MT9071 transmit data
normally. This input is typically set to zero during initial power up, then set to one.
Reset (CMOS compatible input).
When zero, all four transceivers of the MT9071
are in a reset condition where all registers are set to their default values. When
one, all four transceivers of the MT9071 operate normally where all registers may
be programmed by the external processor. A valid reset condition requires this
input to be held low for a minimum of 100ns. This input is should be set to zero
during initial power up, then set to one.
P3
37
TAIS
T1
39
RESET
Pin Description (continued)
LBGA
Pin
LQFP
Pin
Name
Description (see notes 1, 2, 3 and 4)
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| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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