
Preliminary Information
MT9071
61
connect up to 32 transceiver CSTi/CSTo streams together, to accommodate a single common channel
signaling resource such as a 32 channel HDLC controller.
9.2.1
See Table 18 - E1 PCM30 & ST-BUS CSTi/CSTo Timeslot Relationship.
T1 CCS & ST-BUS CSTi/CSTo Timeslot Relationship
10.0 CAS Operation
10.1 T1 CAS
Channel Associated Signaling (CAS) is also referred to as robbed bit signaling. The purpose of CAS is to
provide a scheme that will allow the association of a specific ABCD (or AB) signaling nibble with the
appropriate DS0 channel. The AB signaling bits from frames 6 and 12, or the ABCD signaling bits from frames
6, 12, 18 and 24 are mapped to storage rams and to the serial ST-BUS data stream.
10.1.1
T1 CAS Register and ST-BUS Access
For CAS operation, the robbed bit enable control register bit RBEN (see Table 86 - T1 Signalling Control - R/W
Address Y04) must be set to one. In addition, CAS operation must be enabled on a per channel basis by
setting the clear channel per timeslot control register bit CC (see Table 166 - T1 Per Channel 1 to 24 Control
Registers - R/W Address Y90-YA7) to zero.
Access to the ABCD transmit and receive bits may be either through ST-BUS channels 1 to 24 at the CSTi and
CSTo pins, or through transmit data registers (see Table 162 - T1 Transmit CAS Data Registers - R/W Address
Y50-Y67) and receive data registers (see Table 164 - T1 Receive CAS Data Registers - R Address Y70-Y87)
accessed by the parallel processor port, or through a mix of both methods.
The timeslot control register bits MPST(0-23) (see Table 166 - T1 Per Channel 1 to 24 Control Registers - R/W
Address Y90-YA7) determine the source of the CAS data on a per channel basis. If zero, the transmit signaling
information is constantly updated with the information from the equivalent channel on CSTi, if one, the transmit
CAS data register are the source. Note that when changing the MPST(0-23) control register bits from ST-BUS
source to register source on the fly (during normal operation as opposed to during power up), the transmit CAS
data registers are updated one frame after the timeslot control register bits MPST(0-23) are changed. This is
because the timeslot control register bits do not take effect immediately. Both destinations of CAS data are
always enabled (i.e. ST-BUS CSTo and receive CAS data registers). The receive signaling bits are always
mapped to the equivalent ST-BUS channels on CSTo (see Table 19 - T1 CAS & ST-BUS CSTi/CSTo Timeslot
Relationship).
PCM30 Timeslot
Any one, two or three timeslots of 15, 16 & 31
ST-BUS 2.048Mb/s CSTi/CSTo Timeslot
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 18 - E1 PCM30 & ST-BUS CSTi/CSTo Timeslot Relationship
DS1 Timeslot or Channel
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NA
ST-BUS 2.048Mb/s CSTi/CSTo Timeslot
0 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 z
Table 19 - T1 CAS & ST-BUS CSTi/CSTo Timeslot Relationship
z
z
z
z
z
z
z