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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 159/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
159
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MFL15
MFL14
MFL13
MFL12
MFL11
MFL10
MFL9
MFL8
MFL7
MFL6
MFL5
MFL4
MFL3
MFL2
MFL1
MFL0
Multiframe Out of Frame Count Latch.
These bits make up a latch which samples the current
value of the corresponding counter (T1 Multiframe Out of Frame Counter - R/W Address Y16) on
the rising edge of the internal one second timer status bit ONESEC (T1 Timer Status - R Address
Y11). MFL0 is the least significant bit (LSB). This latch is cleared with either:
a) A hard reset (RESET pin)
b) A unique soft reset (RST bit detailed in Table 178 - T1 Interrupt and I/O Control - R/W
Address YF1)
c) A global soft reset (RSTC bit detailed in Table 70 - T1 & E1 Global Mode Control - R/W
Address 900)
Table 147 - T1 Multiframe Out of Frame Counter Latch - R Address Y2C
Bit
Name
Functional Description
15-9 (0000 000) Not Used
8
GAI
(0)
Go Ahead Interrupt.
This bit is one when the corresponding GAL bit in the T1 & E1 HDLC
Latched Status - R Address Y23 is set, and the corresponding GAM bit in the T1 & E1 HDLC
Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
End of Packet Detect Interrupt.
This bit is one when the corresponding EOPDL bit in the T1
& E1 HDLC Latched Status - R Address Y23 is set, and the corresponding EOPDM bit in the
T1 & E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Transmit End of Packet Interrupt.
This bit is one when the corresponding TEOPL bit in the
T1 & E1 HDLC Latched Status - R Address Y23 is set, and the corresponding TEOPM bit in
the T1 & E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
End of Packet Read Interrupt.
This bit is one when the corresponding EOPRL bit in the T1 &
E1 HDLC Latched Status - R Address Y23 is set, and the corresponding EOPRM bit in the T1
& E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Transmit FIFO Low Interrupt.
This bit is one when the corresponding TXFLL bit in the T1 &
E1 HDLC Latched Status - R Address Y23 is set, and the corresponding TXFLM bit in the T1 &
E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Frame Abort Interrupt.
This bit is one when the corresponding FAL bit in the T1 & E1 HDLC
Latched Status - R Address Y23 is set, and the corresponding FAM bit in the T1 & E1 HDLC
Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
Transmit FIFO Empty Interrupt.
This bit is one when the corresponding TXUNDERL bit in the
T1 & E1 HDLC Latched Status - R Address Y23 is set, and the corresponding TXUNDERM bit
in the T1 & E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Table 148 - T1 & E1 HDLC Interrupt Status - R Address Y33
7
EOPDI
(0)
6
TEOPI
(0)
5
EOPRI
(0)
4
TXFLI
(0)
3
FAI
(0)
2
TXFEI
(0)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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