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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 160/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
160
1
RXFHI
(0)
Receive FIFO High Interrupt.
This bit is one when the corresponding RXFFL bit in the T1 &
E1 HDLC Latched Status - R Address Y23 is set, and the corresponding RXFFM bit in the T1 &
E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Receive FIFO Overflow Interrupt.
This bit is one when the corresponding RXOVFLL bit in the
T1 & E1 HDLC Latched Status - R Address Y23 is set, and the corresponding RXOVFLM bit in
the T1 & E1 HDLC Interrupt Mask - R/W Address Y43 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Table 148 - T1 & E1 HDLC Interrupt Status - R Address Y33
0
RXFOI
(0)
Bit
Name
Functional Description
15
BEOI
(0)
Framing Bit Error Counter Overflow Interrupt.
This bit is one when the corresponding BEOL
bit in the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding
BEOM bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
CRC-6 Error Counter Overflow Interrupt.
This bit is one when the corresponding CEOL bit in
the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding CEOM bit
in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Out Of Frame Counter Overflow Interrupt.
This bit is one when the corresponding OFOL bit in
the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding OFOM bit
in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Change of Frame Alignment Counter Overflow Interrupt
. This bit is one when the
corresponding CFOL bit in the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the
corresponding CFOM bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is
unmasked. This bit is cleared when either this register, or the latched status register is read.
Bipolar Violation Counter Overflow Interrupt.
This bit is one when the corresponding VEOL bit
in the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding VEOM
bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
PRBS Error Counter Overflow Interrupt.
This bit is one when the corresponding PEOL bit in
the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding PEOM bit
in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Multiframe Counter Overflow Interrupt.
This bit is one when the corresponding PCOL bit in the
T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding PCOM bit in
the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Multiframes Out Of Sync Overflow Interrupt.
This bit is one when the corresponding MFOL bit
in the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding MFOM
bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Terminal Frame Synchronization Interrupt.
This bit is one when the corresponding TFSYNL bit
in the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding TFSYNM
bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Table 149 - T1 Receive and Sync Interrupt Status - R Address Y34
14
CEOI
(0)
13
OFOI
(0)
12
CFOI
(0)
11
VEOI
(0)
10
PEOI
(0)
9
PCOI
(0)
8
MFOI
(0)
7
TFSYNI
(0)
Bit
Name
Functional Description
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