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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 79/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
79
register address Y90 of the first per channel control register contains program control for transmit channel 1
and DSTo timeslot 0.
16.3.1
T1 Per Channel Trunk Conditioning
The received data on a DSTo timeslot can be replaced by the idle code data bits RXIDC7-0 detailed in Table 96
- T1 Receive Idle Code Data - R/W Address Y09 on a per channel basis when programmed with control
register bit MPDR in the per channel control registers detailed in Table 166 - T1 Per Channel 1 to 24 Control
Registers - R/W Address Y90-YA7.
Similarly, the transmitted data from a DSTi timeslot can be replaced by the idle code data bits TXIDC7-0
detailed in Table 98 - T1 Transmit Idle Code Data - R/W Address Y0A on a per channel basis when
programmed with control register bit MPDT in the per channel control registers detailed in Table 166 - T1 Per
Channel 1 to 24 Control Registers - R/W Address Y90-YA7.
The received data on a DSto timeslot can also be inverted on a per channel basis by setting control bit RPCI
detailed in Table 166 - T1 Per Channel 1 to 24 Control Registers - R/W Address Y90-YA7.
Similarly, the transmitted data from a DSTi timeslot can also be inverted on a per channel basis by setting
control bit TPCI detailed in Table 166 - T1 Per Channel 1 to 24 Control Registers - R/W Address Y90-YA7.
16.3.2
T1 Per Channel Looping
See Section 15.0 Loopbacks.
16.3.3
T1 Per Channel PRBS Testing
The MT9071 includes both a pseudo random bit sequence (PRBS) generator of type (2
15
-1), and a reverse
PRBS generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted
PRBS type (2
15
-1). Bits which don’t match are counted by an internal error counter. This provides for powerful
system debugging and testing without additional external hardware.
If control register bit ADSEQ (see Table 80 - T1 Line Coding Control - R/W Address Y01) is zero, any transmit
(internal DSTi) timeslot or combination of transmit timeslots may be connected to the PRBS generator.
Timeslot n is selected by setting the TTSTn bit detailed in Table 166 - T1 Per Channel 1 to 24 Control Registers
- R/W Address Y90-YA7, where n is 0 to 23. Any data sent on DSTi is overwritten on the selected timeslots
before being output to TTIP/TRNG.
Similarly, if control register bit ADSEQ is zero, any receive timeslot or combination of receive timeslots may be
connected to the PRBS decoder. Timeslot n is selected by setting the RRSTn bit detailed in Table 166 - T1 Per
Channel 1 to 24 Control Registers - R/W Address Y90-YA7, where n is 0 to 23
PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data
received must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the
data.
If one channel is tested at a time, then the PRBS transmit timeslot does not have to match the PRBS receive
timeslot. However, if more than one channel is tested, then the number of transmit timeslots must match the
number of receive timeslots, and the order of the transmit timeslots must match the order of the receive
timeslots. This will ensure that the sequential data bytes received by the PRBS decoder are in the correct
order. Consequently, particular care must be taken when using an external loopback where the channel order
may be reversed, or where the data has passed through a digital switch which doesn’t buffer all channels to the
same degree.
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