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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 52/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
52
B8ZS decoding, but before passing through the elastic buffer. The output data is synchronous with the
extracted clock (RxCK pin) output. Also synchronous with this output is the basic frame pulse provided at the
RxBF pin output. This output can be used to identify the basic frame boundary of the RxD output data.
6.2
E1 Slip Buffer
In E1 mode, the MT9071 contains one slip buffer on the receive side which may perform a controlled slip.
6.2.1
E1 Receive Slip Buffer
In E1 mode, the MT9071 has a two frame receive elastic (or slip) buffer, which absorbs wander and low
frequency jitter in multi-trunk applications. If desired, the elastic buffer can be bypassed (see Section 6.2.2 E1
Receive Slip Buffer Bypass). The received PCM30 data (RTIP and RRNG) is clocked into the elastic buffer with
the extracted (RxCK pin) clock and is clocked out of the elastic buffer with the system (CKb pin) clock. The
RxCK clock is generated from the receive PCM30 data, and is therefore phase-locked with that data. In ideal
operation (no wander or jitter), the RxCK clock will be phase-locked to the CKb clock, the receive data will be in
phase with the RxCK clock, and the read and write positions of the elastic buffer will remain fixed with respect
to each other.
In a multi-trunk slave or loop-timed system (i.e., PABX application), a single trunk is chosen as a network
synchronizer, where one RxCK clock is used as the reference source for the internal phase locked loop (PLL)
which generates the system clock. In this case for the chosen single trunk, the elastic buffer will function as
described in the previous paragraph.
The remaining trunks will use the system timing derived from the synchronizer to clock data out of their slip
buffers. Even though the PCM30 signals from the network are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the RxCK clocks of non-synchronizer trunks may wander with respect to
the RxCK clock of the synchronizer and the system bus.
Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the
presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9071 will
allow +/- 26 channels (416 UI peak-to-peak) of wander and low frequency jitter before a frame slip will occur.
The minimum delay through the receive slip buffer is approximately 2 channels and the maximum delay is
approximately 60 channels (see Figure 13 - Read and Write Pointers in the E1 Slip Buffers).
When the CKb and the RxCK clocks are not phase-locked, the rate at which data is being written into the slip
buffer from the PCM30 side may differ from the rate at which it is being read out onto the ST-BUS. If this
situation persists, the delay limits stated in the previous paragraph will be violated and the slip buffer will
perform a controlled frame slip. That is, the buffer pointers will be automatically adjusted so that a full PCM30
frame is either repeated or lost. All frame slips occur on PCM30 frame boundaries.
A slip will cause the following events to occur:
The status register bit RSLP will toggle (see Table 105 - E1 Synchronization & CRC-4 Remote Status -
R Address Y10).
The latched status register bit RSLPL = 1 (see Table 133 - E1 Sync Latched Status - R Address Y24).
The interrupt status register bit RSLPI = 1 (see Table 150 - E1 Sync Interrupt Status - R Address Y34),
if unmasked with mask control register bit RSLPM = 0 (see Table 157 - E1 Sync Interrupt Mask - R/W
Address Y44).
The direction of the slip is indicated with status register bit RSLPD (see Table 105 - E1 Synchronization &
CRC-4 Remote Status - R Address Y10). If RSLPD=0, the slip buffer has overflowed and a frame was lost; if
RSLPD=1, an underflow condition occurred and a frame was repeated.
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| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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