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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 62/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
62
The lower nibble of a CSTi/CSTo timeslot is used for the four signaling bits, the upper nibble on the CSTo
timeslots is not used and is either high or low. All unused CSTo timeslots are high impedance. In order to
facilitate multiplexing on the CSTo control streams, control register bit CSToEn (Table 178 - T1 Interrupt and I/
O Control - R/W Address YF1) will place the whole stream in a high impedance state when set low.
In the case of D4 trunks, only AB bits are reported. The control register bits SM1-0 (Table 86 - T1 Signalling
Control - R/W Address Y04) allow the user to program the 2 unused bits (CD) reported on CSTo.
A receive signaling bit debounce of 6ms can be selected with control register bit RSDB (Table 86 - T1
Signalling Control - R/W Address Y04).
It should be noted that there may be as much as 3ms added to this
duration because signaling equipment state changes are not synchronous with the D4 or ESF multiframe.
If multiframe synchronization is lost, as indicated by status register bit MFSYNC =1 (Table 104 - T1
Synchronization and Alarm Status - R Address Y10), then the CAS bits will be frozen (i.e. will retain their
previous value and will not be updated). The CAS bits are unfrozen when multiframe synchronization is
acquired (this is the same as terminal frame synchronization for ESF links).
CAS signaling freeze due to receiver slip is also available by setting control register bit RFS =1 (Table 86 - T1
Signalling Control - R/W Address Y04).
A CAS state change on any of the 24 receive channels will cause the following events to occur:
The latched status register bit CASRL = 1 (see Table 134 - T1 Receive Line Status and Timer Latch - R
Address Y25).
The interrupt status register bit CASRI = 1 (see Table 151 - T1 Receive Line and Timer Interrupt Status
- R Address Y35), if unmasked with mask control register bit CASRM = 0 (see Table 158 - T1 Receive
Line and Timer Interrupt Mask - R/W Address Y45).
When the CASRI interrupt is unmasked, IRQ will become active when a signaling state change is detected in
any of the 24 receive channels and the selectable 1/4/8/16 msec timer (see control bits SIP1,0 detailed Table
86 - T1 Signalling Control - R/W Address Y04) has expired. This function helps to reduce the frequency of
interrupts generated due to signaling changes. For instance if 7 channels had a signaling change, only one
interrupt will be generated in a 1/4/8/16 msec duration. Upon an interrupt, the user has to read the CAS
registers (Table 164 - T1 Receive CAS Data Registers - R Address Y70-Y87) to determine the channels with a
signaling change. Any channels marked as clear channels will not generate an interrupt due to changes in
ABCD bits.
10.2 E1 CAS
The purpose of the CAS Multiframing algorithm is to provide a scheme that will allow the association of a
specific ABCD signaling nibble with the appropriate PCM30 channel. A CAS multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a multiframe repetition rate of 2ms. It should be noted that the
boundaries of the signaling multiframe may be completely distinct from those of the CRC-4 multiframe. CAS
multiframe alignment is based on a multiframe alignment signal (a 0000 bit sequence), which occurs in the
most significant nibble of timeslot 16 of basic frame 0 of the CAS multiframe. Bits 5, 7 and 8 (usually
designated X) are spare bits and are normally set to one if not used. Bit 6 of this timeslot is the multiframe
alarm bit (usually designated Y). When CAS multiframing is acquired on the receive side, the transmit Y-bit is
zero; when CAS multiframing is not acquired, the transmit Y-bit is one. Refer to ITU-T G.704 and G.732 for
more details on CAS multiframing requirements.
Timeslot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) are reserved for
the ABCD signaling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1
to 15 and the least significant nibbles are reserved for channels 16 to 30. That is, timeslot 16 of basic frame 1
has ABCD for channel 1 and 16, timeslot 16 of basic frame 2 has ABCD for channel 2 and 17, through to
timeslot 16 of basic frame 15 has ABCD for channel 15 and 30. See Table 20 - E1 CAS Multiframe Structure.
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PDF描述 |
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| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開(kāi)關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開(kāi)關(guān)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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