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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 152/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
152
12
FEIL
Frame
corresponding counter (E1 FAS Bit Error Counter & FAS Error Counter - R/W Address Y1A)
is incremented by one, this status bit is latched to one. It is cleared when either this
register, or the E1 Counter Interrupt Status - R Address Y35 is read.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Latch.
When the corresponding
counter (E1 FAS Bit Error Counter & FAS Error Counter - R/W Address Y1A) overflows to 0,
this status bit is latched to one. It is cleared when either this register, or the E1 Counter
Interrupt Status - R Address Y35 is read.
Frame Alignment Signal (FAS) Bit Error Counter Indication Latch.
When the
corresponding counter (E1 FAS Bit Error Counter & FAS Error Counter - R/W Address Y1A) is
incremented by one, this status bit is latched to one. It is cleared when either this register, or
the E1 Counter Interrupt Status - R Address Y35 is read.
CRC-4 Error Counter Overflow Latch.
When the corresponding counter (E1 CRC-4 Error
Counter - R/W Address Y19) overflows to 0, this status bit is latched to one. It is cleared when
either this register, or the E1 Counter Interrupt Status - R Address Y35 is read.
CRC-4 Error Counter Indication Latch.
When the corresponding counter (E1 CRC-4 Error
Counter - R/W Address Y19) is incremented by one, this status bit is latched to one. It is
cleared when either this register, or the E1 Counter Interrupt Status - R Address Y35 is read.
Bipolar Violation Error Counter Overflow Latch.
When the corresponding counter (E1
Bipolar Violation Error Counter - R/W Address Y18) overflows to 0, this status bit is latched to
one. It is cleared when either this register, or the E1 Counter Interrupt Status - R Address Y35
is read.
Bipolar Violation Error Counter Indication Latch.
When the corresponding counter (E1
Bipolar Violation Error Counter - R/W Address Y18) is incremented by one, this status bit is
latched to one. It is cleared when either this register, or the E1 Counter Interrupt Status - R
Address Y35 is read.
E-Bit Error Counter Overflow Latch.
When the corresponding counter (E1 E-bit Error
Counter - R/W Address Y17) overflows to 0, this status bit is latched to one. It is cleared when
either this register, or the E1 Counter Interrupt Status - R Address Y35 is read.
E-Bit Error Counter Indication Latch.
When the corresponding counter (E1 E-bit Error
Counter - R/W Address Y17) is incremented by one, this status bit is latched to one. It is
cleared when either this register, or the E1 Counter Interrupt Status - R Address Y35 is read.
PRBS CRC-4 Counter Overflow Latch.
When the corresponding counter (E1 PRBS Error
Counter & PRBS CRC Multiframe Counter - R/W Address Y15) overflows to 0, this status bit is
latched to one. It is cleared when either this register, or the E1 Counter Interrupt Status - R
Address Y35 is read.
Jitter Attenuator Latch.
This status bit is latched to one when either the JAF4 status bit
toggles from one to zero, or the JAE4 status bit toggles from zero to one. These status bits are
detailed in the T1 & E1 LIU and JA Status - R Address YE0. It is cleared when either this
register, or the E1 Counter Interrupt Status - R Address Y35 is read.
PRBS Error Counter Overflow Latch.
When the corresponding counter (E1 PRBS Error
Counter & PRBS CRC Multiframe Counter - R/W Address Y15) overflows to 0, this status bit is
latched to one. It is cleared when either this register, or the E1 Counter Interrupt Status - R
Address Y35 is read.
PRBS Error Counter Indication Latch.
When the corresponding counter (E1 PRBS Error
Counter & PRBS CRC Multiframe Counter - R/W Address Y15) is incremented by one, this
status bit is latched to one. It is cleared when either this register, or the E1 Counter Interrupt
Status - R Address Y35 is read.
Table 135 - E1 Counter Latched Status - R Address Y25
Alignment
Signal
(FAS)
Error
Counter
Indication
Latch.
When
the
11
BEOL
10
BEIL
9
CEOL
8
CEIL
7
VEOL
6
VEIL
5
EEOL
4
EEIL
3
PCOL
2
JAL
1
PEOL
0
PEIL
Bit
Name
Functional Description
相關(guān)PDF資料 |
PDF描述 |
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| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開(kāi)關(guān)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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