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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 69/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
69
11.2.5
E1 Data Link 5 Bit Register Access
Receive only 5 bit data register bits RNU4-8. See Table 111 E1 NFAS Signal and FAS Status - R Address Y13.
12.0 HDLC
The MT9071 has four embedded HDLC controllers, one for each of the four transceiver’s, each of which
includes the following features:
Independent transmit and receive FIFO's;
Receive FIFO maskable interrupts for nearly full (programmable interrupt levels) and overflow
conditions;
Transmit FIFO maskable interrupts for nearly empty programmable interrupt levels) and underflow
conditions;
Maskable interrupts for transmit end-of-packet and receive end-of-packet;
Maskable interrupts for receive bad-frame (includes frame abort);
Transmit end-of-packet and frame-abort functions.
In E1 mode, each controller may be attached to a data link operating at 4, 8, 12, 16 or 20kb/s for the Sa4, Sa5,
Sa6, Sa7 and or Sa8 data link bits of timeslot 0 of the PCM30 frame.
In T1 mode, each controller may be attached to a data link operating at 4kb/s for the synchronization bit (s-bit)
of the DS1 frame.
In addition, in E1 or T1 mode, each controller may be attached to a common channel signaling channel
operating at 64kb/s for any T1 or E1 channel (not including timeslot 0 for E1 mode).
12.1 HDLC Overview
The HDLC handles the bit oriented packetized data transmission as per X.25 level two protocol defined by
CCITT. It provides flag and abort sequence generation and detection, zero insertion and deletion, and Frame
Check Sequence (FCS) generation and detection. A single byte, dual byte and all call address in the received
frame can be recognized. Access to the receive FCS and inhibiting of transmit FCS for terminal adaptation are
also provided. Each HDLC controller has a 32 byte deep FIFO associated with it. Status and interrupt flags are
provided.
12.1.1
HDLC Frame Structure
In T1 mode or E1 mode a valid HDLC frame begins with an opening flag, contains at least 16 bits of address
and control or information, and ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner
is also referred to as a “packet”. Refer to Table 26 - HDLC Frame Format.
All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags
and appends them to the packet to be transmitted. The receiver searches the incoming data stream for the
flags on a bit- by-bit basis to establish frame synchronization.
The data field consists of an address field, control field and information field. The address field consists of one
or two bytes directly following the opening flag. The control field consists of one byte directly following the
address field. The information field immediately follows the control field and consists of N bytes of data. The
Opening Flag = 7E hex
Data Field
FCS
Closing Flag = 7E hex
One Byte
01111110
n Bytes
n 2
Table 26 - HDLC Frame Format
Two Bytes
One Byte
01111110
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級(jí)通道開關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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