
Preliminary Information
MT9071
25
1.0
Device Overview
The MT9071 is a four port (quad) long/short haul T1/E1/J1 transceiver with an integrated reference switching
PLL. Each of the four transceivers has one embedded HDLC (High-level Data Link Controller) that can be
assigned to the maintenance channel or to any other channel.
1.1
Standards Compliance
In T1 mode the MT9071 meets or supports the latest recommendations including AT&T PUB43801, TR-62411;
ANSI T1.102, T1.403 and T1.408; ITU-T G.802. It also supports Telcordia GR-303-CORE. In T1 ESF mode the
CRC-6 calculation and yellow alarm can be configured to meet the requirements of a J1 interface.
In E1 mode the MT9071 meets or supports the latest ITU-T Recommendations for PCM30 and ISDN primary
rate including G.703, G.704, G.706, G.732, G.775, G.796, G.823, G.964 (V5.1), G.965 (V5.2) and I.431. It also
meets or supports ETSI TBR4, TBR13, ETS 300 233, ETS 300 324 (V5.1) and ETS 300 347 (V5.2).
1.2
Microprocessor Port
A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and
status registers.
1.3
LIU
The MT9071 LIU interfaces the digital framer functions to a T1 or E1 transformer-isolated four wire line.
In T1 mode, the LIU can pre-equalize the transmit signal to meet the T1.403 and T1.102 pulse templates after
attenuation by 0 - 655 feet of 22 AWG PIC cable, alternatively it can provide line build outs of 7.5dB, 15dB and
22.5dB. In T1 mode the receiver can recover signals attenuated by up to 36dB at 772kHz.
In E1 mode, the LIU transmits signals that meet the G.703 2.048 Mbit/s pulse template and the receiver can
recover signals attenuated by up to 40dB at 1024kHz.
1.4
Reference Switching PLL
The MT9071 PLL can switch its source of network synchronization from between the four internal LIUs and/or
an external timing source without causing bit errors or loss of frame synchronization. During a reference switch
the MTIE (Maximum Time Interval Error) and the phase slope comply with the limits recommended in Telcordia:
GR-1244-CORE for a Stratum 3 clock, and ITU-T G.812 for a Type IV clock. In the event of reference loss, the
PLL enters holdover mode with frequency accuracy of 0.05ppm.
The MT9071 PLL attenuates jitter from 1.9 Hz with a roll-off of 20 dB/decade. The intrinsic jitter is less than
0.02 UI. In all timing modes the low jitter output of the PLL provides timing to the transmit side of the four LIUs.
1.5
Slip Buffers
In T1 mode, the receive and transmit paths both include two-frame slip buffers. The transmit slip buffer delay is
programmable.
In E1 mode, the receive path includes a two-frame slip buffer and the transmit path contains a 128 bit Jitter
Attenuator (JA) FIFO with programmable depth.