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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 46/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
46
considered to be a non-CRC-4 interface. When the distant end is a non-CRC-4 interface, the near end
automatically suspends receive CRC-4 functions, continues to transmit CRC-4 data to the distant end with its
E-bits set to zero, and provides a status indication. Naturally, if the distant end initially achieves CRC-4
synchronization, CRC-4 processing will be carried out by both ends.
When control register bit AUTC is one, Automatic CRC-4 Interworking is deactivated. In this case, if control
register bit ARAI (see Table 79 - E1 Alarms and Framing Control - R/W Address Y00) is low, and if CRC-4
multiframe alignment is not found in 400ms, then the transmit RAI will be continuously high until CRC-4
multiframe alignment is achieved.
The transmit E bits control register bit TE (see Table 79 - E1 Alarms and Framing Control - R/W Address Y00)
will have the same function in both states of AUTC. That is, when CRC-4 synchronization is not achieved the
state of the transmit E-bits will be the same as the state of the TE control register bit. When CRC-4
synchronization is achieved, the transmit E-bits will function as per ITU-T G.704 as (see Section 5.4.2 E1 CRC-
4 Multiframing, Table 9 -E1 Operation of AUTC, ARAI and TALM Control Register Bits, and Table 10 - E1 CRC
Interworking Status Register Bits).
Register Bits
Description
AUTC ARAI TALM
Before the 400ms Timer Expires
After the 400ms Timer Expires
No Valid CRC
MFAS
Valid CRC
MFAS
0
0
X
If no valid CRC
MFAS is being
received, the
device will search
for a new basic
frame alignment
signal every 8ms
for 400ms. During
this cycle, the
transmit RAI will
flicker high with
every reframe
(8ms).
If a valid CRC
MFAS is
receivedduring
the 400ms
period, the
device will set
status register
bitsCSYNCB=
0, CRCIW = 1
as (see Table
105 - E1
Synchronizatio
n & CRC-4
Remote Status
- R Address
Y10), and will
set the transmit
E-bits as per
G.703 and will
send RAI low
continuously.
Following the 400ms, the device will continue to transmit
CRC-4 remainders, will set the transmit E-bits to be the
same state as the TE control register bit (see Table 79 -
E1 Alarms and Framing Control - R/W Address Y00),
will send RAI low continuously, and will indicate CRC-to-
non-CRC operation with status register bit CRCIW = 0
(see Table 105 - E1 Synchronization & CRC-4 Remote
Status - R Address Y10).
The device will continue searching for CRC MFAS,
however, the above operation (CRC-to-non-CRC) will
not change if CRC MFAS sync is found, as indicated
with status register bits CSYNCB = 0, CRCIW = 0 (see
Table 105 - E1 Synchronization & CRC-4 Remote
Status - R Address Y10).
Following the 400ms, the device will continue to transmit
CRC-4 remainders, will set the transmit E-bits to be the
same state as the TE control register bit (see Table 79 -
E1 Alarms and Framing Control - R/W Address Y00),
will send RAI high continuously, and will indicate that it
is attempting CRC-to-CRC operation with status register
bit CRCIW = 1 (see Table 105 - E1 Synchronization &
CRC-4 Remote Status - R Address Y10).
1
0
X
The device will continue searching for CRC MFAS, and
if found, will set status register bits CSYNCB = 0,
CRCIW = 1 as (see Table 105 - E1 Synchronization &
CRC-4 Remote Status - R Address Y10), and will set
the transmit E-bits as per G.703 and will send RAI low
continuously
X
X
1
1
0
1
Transmit RAI is low continuously.
Transmit RAI is high continuously.
Table 9 - E1 Operation of AUTC, ARAI and TALM Control Register Bits
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