參數資料
型號: MT9071
廠商: Mitel Networks Corporation
英文描述: Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器(集成四個獨立幀調節(jié)器))
中文描述: 四T1/E1/J1收發(fā)器(多端口的T1/E1/J1幀調節(jié)器(集成四個獨立幀調節(jié)器))
文件頁數: 171/217頁
文件大?。?/td> 686K
代理商: MT9071
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Preliminary Information
MT9071
171
Bit
Name
Functional Description
15
14
(0)
Not Used
Loss of Sync Counter Overflow Mask.
This is the mask bit for the corresponding SLOI bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Frame Alignment Signal (FAS) Error Counter Overflow Mask.
This is the mask bit for the
corresponding FEOI bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit is
one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function
normally.
Frame Alignment Signal (FAS) Error Counter Indication Mask.
This is the mask bit for the
corresponding FEII bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit is
one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function
normally.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Mask.
This is the mask bit for
the corresponding BEOI bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit
is one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function
normally.
Frame Alignment Signal (FAS) Bit Error Counter Indication Mask.
This is the mask bit for
the corresponding BEII bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit
is one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function
normally.
CRC-4 Error Counter Overflow Mask.
This is the mask bit for the corresponding CEOI bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
CRC-4 Error Counter Indication Mask.
This is the mask bit for the corresponding CEII bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Bipolar Violation Error Counter Overflow Mask.
This is the mask bit for the corresponding
VEOI bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Bipolar Violation Error Counter Indication Mask.
This is the mask bit for the corresponding
VEII bit in the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
E-Bit Error Counter Overflow Mask.
This is the mask bit for the corresponding EEOI bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
E-Bit Error Counter Indication Mask.
This is the mask bit for the corresponding EEII bit in the
E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
PRBS CRC-4 Counter Overflow Mask.
This is the mask bit for the corresponding PCOI bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Jitter Attenuator Mask.
This is the mask bit for the corresponding JAI bit in the E1 Counter
Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will remain inactive. If
this mask bit is zero, the interrupt bit will function normally.
PRBS Error Counter Overflow Mask.
This is the mask bit for the corresponding PEOI bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
PRBS Error Counter Indication Mask.
This is the mask bit for the corresponding PEII bit in
the E1 Counter Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Table 159 - E1 Counter Interrupt Mask - R/W Address Y45
SLOM
(0)
13
FEOM
(0)
12
FEIM
(0)
11
BEOM
(0)
10
BEIM
(0)
9
CEOM
(0)
8
CEIM
(0)
7
VEOM
(0)
6
VEIM
(0)
5
EEOM
(0)
4
EEIM
(0)
3
PCOM
(0)
2
JAM
(0)
1
PEOM
(0)
0
PEIM
(0)
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