
MT9071
Preliminary Information
78
16.2 T1 Error Insertion
Six types of error conditions can be inserted into the transmit DS1 data stream through control register bits,
which are detailed in Table 84 - T1 Transmit Error Control - R/W Address Y03. These error events include the
bipolar violation errors (BPVE), CRC-6 errors (CRCE), Ft errors (FTE), Fs errors (FSE), payload (PERR) and a
loss of signal condition (LOSE). If LOSE is one, the MT9071 transmits an all zeros signal (no pulses). Zero
code suppression is overridden. If LOSE bit is zero, data is transmitted normally.
16.3 T1 Per Channel Control
There are 24 per channel control registers occupying a total of 24 unique addresses (see Table 166 - T1 Per
Channel 1 to 24 Control Registers - R/W Address Y90-YA7). Each register controls a matching timeslot on the
24 transmit channels (onto the line) and the equivalent channel data on the receive (DSTo) data. For example,
Counter
Counter 1 Sec. Latch
Counter Indication
Counter Overflow
Latch
Int.
Mask Latch
Int.
Mask
Table 114 - T1 PRBS CRC
Multiframe and PRBS Error
Counter - R/W Address Y15
PCC7-0
PEC7-0
Table 116 - T1 Multiframe Out
of Frame Counter - R/W
Address Y16
MFC15-0
Table 118 - T1 Framing Bit Error
Counter - R/W Address Y17
BEC15-0
Table 120 - T1 Bipolar Violation
Counter - R/W Address Y18
NA
NA
Y25
NA
Y35
NA
Y45
Y24
Y24
Y34
Y34
Y44
Y44
NA
PEIL
NA
PEII
NA
PEIM
PCOL
PEOL
Y24
PCOI
PEOI
Y34
PCOM
PEOM
Y44
Table 147 - T1 Multiframe Out of
Frame Counter Latch - R Address
Y2C
MFL15-0
Table 139 - T1 Framing Bit Error
Counter Latch - R Address Y28
BEL15-0
Table 141 - T1 Bipolar Violation
Error Counter Latch - R Address
Y29
VEL15-0
Table 143 - T1 CRC-6 Error
Counter Latch - R Address Y2A
CEL15-0
Table 145 - T1 Out of Frame &
Change of Frame Counter Latch -
R Address Y2B
OFL7-0
CFL7-0
NA
MFOL MFOI MFOM
Y24
Y34
Y24
Y34
Y44
Y44
BEIL
Y25
BEII
Y35
BEIM BEOL BEOI BEOM
Y45
Y24
Y34
Y44
VEC15-0
VEIL
Y24
VEII
Y34
VEIM VEOL VEOI VEOM
Y44
Y24
Table 122 - T1 CRC-6 Error
Counter - R/W Address Y19
CEC15-0
Table 124 - T1 Out of Frame
and Change of Frame Counters
- R/W Address Y1A
OFC7-0
CFC7-0
Table 126 - T1 Excessive Zero’s
Counter - R/W Address Y1B
EZC7-0
Y34
Y44
CEIL
NA
Y24
CEII
NA
Y34
CEIM CEOL CEOI CEOM
NA
Y44
Y24
Y24
Y34
Y34
Y44
Y44
NA
CFIL
Y26
NA
CFII
Y36
NA
CFIM
Y46
OFOL
CFOL
Y26
OFOI
CFOI
Y36
OFOM
CFOM
Y46
NA
EZIL
EZII
EZIM EZOL EZOI
EZOM
Y24 - See Table 132 - T1 Receive Sync and Alarm Latch - R Address Y24
Y25 - See Table 134 - T1 Receive Line Status and Timer Latch - R Address Y25
Y26 - See Table 136 - T1 Elastic Store Status Latch - R Address Y26
Y34 - See Table 149 - T1 Receive and Sync Interrupt Status - R Address Y34
Y35 - See Table 151 - T1 Receive Line and Timer Interrupt Status - R Address Y35
Y36 - See Table 153 - T1 Elastic Store Interrupt Status - R Address Y36
Y44 - See Table 156 - T1 Receive and Sync Interrupt Mask - R/W Address Y44
Y45 - See Table 158 - T1 Receive Line and Timer Interrupt Mask - R/W Address Y45
Y46 - See Table 160 - T1 Elastic Store Interrupt Mask - R/W Address Y46
Table 31 - T1 Error Counters Summary