
MT9071
Preliminary Information
124
1
TS16E
(0)
Time Slot 16 CST Enable.
If one, the transmit PCM30 link timeslot 16 data will be sourced
from a CSTi timeslot as selected by control bits 16C4 to 16C0 detailed in Table 93 - E1 CCS
CSTi and CSTo Map Control - R/W Address Y07. And, the receive PCM30 link timeslot 16 data
will be sourced to both DSTo timeslot 16 and to the above selected CSTo timeslot. This feature
is used to link PCM30 CCS data to an external HDLC device through the CSTo and CSTi pins.
If zero, the transmit PCM30 link timeslot 16 data will be sourced from DSTi timeslot 16. And,
the receive PCM30 link timeslot 16 data will be sourced to DSTo timeslot 16 only.
Common Channel Signaling (CSIG =1 detailed in Table 85 - E1 DL, CCS, CAS and Other
Control - R/W Address Y03) must be selected for these operations to be valid.
Time Slot 15 CST Enable.
If one, the transmit PCM30 link timeslot 15 data will be sourced
from a CSTi timeslot as selected by control bits 15C4 to 15C0 detailed in Table 93 - E1 CCS
CSTi and CSTo Map Control - R/W Address Y07. And, the receive PCM30 link timeslot 15 data
will be sourced to both DSTo timeslot 15 and to the above selected CSTo timeslot. This feature
is used to link PCM30 CCS data to an external HDLC device through the CSTo and CSTi pins.
If zero, the transmit PCM30 link timeslot 15 data will be sourced from DSTi timeslot 15. And,
the receive PCM30 link timeslot 15 data will be sourced to DSTo timeslot 15 only.
0
TS15E
(0)
Common Channel Signaling (CSIG =1 detailed in Table 85 - E1 DL, CCS, CAS and Other
Control - R/W Address Y03) must be selected for these operations to be valid.
Table 91 - E1 HDLC and CCS ST-BUS Control - R/W Address Y06
Bit
Name
Functional Description
15-8 (#### ####) Not Used
7
6
5
4
3
2
1
0
TXBOM0
(0000 0000)
TXBOM7
TXBOM6
TXBOM5
TXBOM4
TXBOM3
TXBOM2
TXBOM1
Transmit Bit Oriented Message.
The contents of this register are concatenated with a
sequence of eight 1’s and are continuously transmitted in the FDL bit position of ESF trunks.
Normally, the first and last bit of this register are set to zero.
Table 92 - T1 Transmit BOM Data - R/W Address Y07
Bit
Name
Functional Description
15
14
13
12
11
10
(#)
31C4
31C3
31C2
31C1
31C0
(11111)
Not Used
Timeslot 31 CST Map Bits.
The selection of these bits results in a mapping of the transmit
PCM30 timeslot 31, from a specific CSTi timeslot; and similarly, maps receive PCM30 timeslot
31, to a specific CSTo timeslot. PCM30 timeslot 31 data is mapped to/from CST channel n
(n=0 to 31), where n is the bcd equivalent of 31C4 to 31C0 with 31C4 being the most
significant bit.
31C4
31C3
31C2
31C1
0
0
0
0
0
0
0
0
etc.
1
1
1
1
Control bit CSIG of E1 DL, CCS, CAS and Other Control - R/W Address Y03, and control bit
TS31E of E1 HDLC and CCS ST-BUS Control - R/W Address Y06 must both be set for these
operations to be valid.
Table 93 - E1 CCS CSTi and CSTo Map Control - R/W Address Y07
31C0
0
1
CST Timeslot
0
1
1
31
Bit
Name
Functional Description