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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 184/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
184
5
MRKID
(0)
Mark-Idle.
When high, the transmitter will be in an interframe time fill state. When low, the
transmitter will be in an idle state.These two states will only occur when the Transmit FIFO is
empty. See Section 12.1.5 Interframe Time Fill and Link Channel States.
Cycle.
When high, the T1 & E1 HDLC Transmit Packet Size - R/W Address YF6 will
continuously cycle through a count up sequence.
Transmit CRC Inhibit.
When high, this bit will inhibit transmission of the CRC. That is, the
transmitter will not insert the computed CRC onto the bit stream after seeing the EOP tag byte.
This is used in V.120 terminal adaptation for synchronous protocol sensitive UI frames.
Seven.
When high, this bit will enable seven bits of address recognition in the first received
address byte. The received address byte must have bit 0 equal to 1 which indicates a single
address byte is being received. See Table 181 T1 & E1 HDLC Address Recognition Control -
R/W Address YF4.
Receive FIFO Reset.
When high, the Receive FIFO will be reset. This causes the receiver to
be disabled until the next reception of a flag. The status register will identify the FIFO as being
empty. However, the actual bit values in the Receive FIFO will not be reset.
Transmit FIFO Reset.
When high, the Transmit FIFO will be reset. The Status Register will
identify the FIFO as being empty. This bit will be reset when data is written to the Transmit
FIFO. However, the actual bit values of data in the Transmit FIFO will not be reset. It is cleared
by the next write to the Transmit FIFO.
Table 179 - T1 & E1 HDLC Control 0 - R/W Address YF2
4
CYCLE
(0)
TCRCI
(0)
3
2
SEVEN
(0)
1
RXFRST
(0)
0
TXFRST
(0)
Bit
Name
Functional Description
15-6 (#### #### ##) Not Used
5
HRST
(0)
4
RTLOOP
(0)
HDLC Reset.
When this bit is set to one, the HDLC will be reset. This bit can only be reset
by writing a zero to this location or applying soft or hard reset.
Receive to Transmit Loopback.
When this bit is high, receive to transmit HDLC loopback
will be activated. Receive data, including end of packet indication, but not including flags or
CRC, will be written to the Transmit FIFO as well as the Receive FIFO. When the transmitter
is enabled, this data will be transmitted as though written by the microprocessor. Both good
and bad packets will be looped back. Receive to transmit loopback may also be
accomplished by reading the Receive FIFO using the microprocessor and writing these
bytes, with appropriate tags, into the Transmit FIFO.
CRC Remainder Test.
When high, direct access to the T1 & E1 HDLC Receive CRC Data -
R/W Address Y1E through the serial interface is enabled. After testing is enabled, serial
data is clocked in until the data aligns with the internal comparison (16 RXCLK clock cycles)
and then the clock is stopped. The expected pattern is F0B8 hex. Each bit of the CRC can
be corrupted to allow more efficient testing.
FIFO Test.
This bit allows the writing to the Receive FIFO and reading of the Transmit FIFO
through the microprocessor to allow more efficient testing of the FIFO status/interrupt
functionality. This is done by making a Transmit FIFO write become a Receive FIFO write
and a Receive FIFO read become a Transmit FIFO read. In addition, EOP/FA and RQ8/RQ9
are re-defined to be accessible (i.e. Receive write causes EOP/FA to go to Receive fifo
input; Transmit read looks at output of Transmit fifo through RQ8/RQ9 bits).
Address Recognition Test.
This bit allows direct access to the Address Recognition
Registers in the receiver through the serial interface to allow more efficient testing. After
address testing is enabled, serial data is clocked in until the data aligns with the internal
address comparison (16 RXc clock cycles) and then clock is stopped.
TR Loopback.
When high, transmit to receive HDLC loopback will be activated. The
packetized transmit data will be looped back to the receive input. RXEN and TXEN bits must
also be enabled.
Table 180 - T1 & E1 HDLC Control 1 - R/W Address YF3
3
CRCTST
(0)
2
FTST
(0)
1
ADTST
(0)
0
HLOOP
(0)
Bit
Name
Functional Description
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