
Preliminary Information
MT9071
35
3.3
Reference Switching
The MT9071 PLL accepts two simultaneous reference input signals referred to as the primary reference signal
and the secondary reference signal. The input reference frequency must match the frequency selected with
control register bits FS2-1 (see Table 73 - T1 & E1 Global Timing Control - R/W Address 905), also refer to
Table 2 - Reference Selection Summary.
A reference switch is made with a two step process using control register bits PR2-0, SR2-0 and RSEL (see
Table 73 - T1 & E1 Global Timing Control - R/W Address 905). First, select a new compatible input reference
source (see Table 73 - T1 & E1 Global Timing Control - R/W Address 905) for the non-current primary or
secondary input with either PR2-0 and SR2-0 respectively. Next, toggle the RSEL control register bit.
For example, if the PLL is currently using primary reference RxCK[3], select a desired secondary reference (i.e.
RxCK[0]) with SR2-0 (without changing the primary reference). Then, after waiting at least one frame (i.e.
125us), toggle RSEL from 0 to 1. Typically, the secondary reference is known and selected well in advance.
3.4
PLL State Changes
For state change details refer to Table 3 - PLL State Table and Figure 7 - PLL State Diagram.
Framer
Mode
PLL
Input Frequency
*Compatible Input Reference Sources
(Must be at the PLL Input Frequency)
Timing
Mode
E1
E1
E1
T1
T1
T1
2.048MHz
1.544MHz
8kHz
2.048MHz
1.544MHz
8kHz
CKb, RxCK[3], RxCK[2], RxCK[1], RxCK[0] or ESYN
ESYN
FPb or ESYN
CKb or ESYN
RxCK[3], RxCK[2], RxCK[1], RxCK[0] or ESYN
FPb or ESYN
Bus, Line or External
External
Bus or External
Bus or External
Line or External
Bus or External
*The Compatible Input Reference Sources must be at the PLL Input Frequency with the exception of CKb. CKb is automatically
divided down to 2.048MHz in both 2.048MHz and 8.192MHz backplane modes.
Table 2 - Reference Selection Summary
Register and Bits
State
T1 & E1 Global Timing
Control - R/W Address 905
Freerun
Normal
(Primary)
Normal
(Secondary)
Holdover
(Primary)
Holdover
(Secondary)
MS2
0
0
0
0
0
1
MS1
0
0
0
1
1
0
RSEL
0
0
1
0
1
X
TIEE
0
1
X
X
X
X
S0
S1
S1
S2
/
/
-
S1
-
-
S2
S1H
S1
S1 MTIE
S2 MTIE
-
/
S0
S2H
S1 MTIE
S1 MTIE
-
/
S2H
S0
S1 MTIE
S1 MTIE
S2 MTIE
/
-
S0
S2 MTIE
S1H
S2H
S0
- No Change
/ Not Valid
MTIE State change occurs with TIE Corrector Circuit
Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State
Table 3 - PLL State Table