
MT9071
Preliminary Information
74
13.2 E1 Transparent Mode Operation
13.2.1
Transmit Timeslot 0 all Frames from DSTi to PCM30
Setting control register bit TXTRS (see Table 85 - E1 DL, CCS, CAS and Other Control - R/W Address Y03)
enables transparent mode operation which causes unframed data to be transmitted from DSTi channels 0 to 31
onto the PCM30 line. Unframed data received from the PCM30 line is piped out on DSTo channels 0 to 31. In
other words, timeslot 0 data on the transmit PCM30 link is sourced from the DSTi input. Table 27 - E1 Transmit/
Receive Timeslot 0 from/to ST-BUS DSTi/DSTo shows the detailed bit mapping of DSTi timeslot 0 to transmit
PCM30 timeslot 0.
13.2.2
Receive Timeslot 0 all Frames from PCM30 to DSTo
Timeslot 0 signal bits on the receive PCM30 link (bit positions one to eight of timeslot 0 of all frames) may be
sourced to either data registers, data buffers, to the ST-BUS DSTo stream, to a modified ST-BUS DSTo stream,
or to a mix of all; depending on the programming of control register bits detailed in Table 167 - E1 Per Timeslot
0 to 31 Control Registers - R/W Address Y90-YAF. If these register bits are disabled, then data to DSTo is
mapped unaltered from the receive PCM30 link as shown in Table 27 - E1 Transmit/Receive Timeslot 0 from/to
ST-BUS DSTi/DSTo.
14.0 Payload Data Operation
14.1 T1 DS1 Payload Data
The T1 DS1 payload usually consists of channels 1 to 24, refer to Section 4.1 T1 Interface Overview.
14.1.1
T1 DS1 & ST-BUS DSTi/DSTo Timeslot Relationship
When mapping to the DS1 payload, only the first 24 time slots of an ST-BUS are used. See Table 28 - T1 DS1
& ST-BUS DSTi/DSTo Timeslot Relationship. Note that ST-BUS timeslot 31 may be used for the framing bit (S-
bit). All unused ST-BUS DSTo timeslots are high impedance.
ST-BUS DSTi/DSTo
PCM30 Transmit/Receive
Frame
Timeslot
Data Bits (B7-B0)
Timeslot
Frame
Data Bits (B1-B8)
All
n
P8, P7, P6, P5, P4, P3, P2, P1 0
All
P1, P2, P3, P4, P5, P6, P7, P8
Note 1. For 2.048Mb/s operation, n=0.
Note 2. For 8.192Mb/s operation, n =0,1,2,3 where n corresponds to the tranceiver number (i.e. n=0=tranceiver 0... n=3= tranceiver
3).
Table 27 - E1 Transmit/Receive Timeslot 0 from/to ST-BUS DSTi/DSTo
DS1 Timeslot or Channel
T
R
A
N
C
E
I
V
E
R
0-3 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S-bit
ST-BUS 2.048Mb/s DSTi/DSTo Timeslot
0-3 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
ST-BUS 8.192Mb/s DSTi/DSTo Timeslot
0
0
4
8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124
1
1
5
9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125
2
2
6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126
3
3
7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 68 75 79 83 87 91 95 99 103 107 111 115 119 123 127
Table 28 - T1 DS1 & ST-BUS DSTi/DSTo Timeslot Relationship