
MT9071
Preliminary Information
114
21.2 T1 & E1 Unique Transceiver Register Bit Functions - in Address Order
Bit
Name
Functional Description
15
RSV
(0)
(#)
G802
(0)
Reserved
. Must be set to 0 for normal operation.
14
13
Not Used
G.802 Mode
. If one, the device operates with embedded framing as per G.802. The backplane
operates at 2.048Mb/s with an E1 PCM30 format. The link operates as a T1 DS1 link. If zero,
device operates normally.
Japan Yellow Alarm
Set this bit high to select a pattern of 16 ones (111111111111111) as the
ESF yellow alarm, both for the case when an ESF yellow alarm is to be transmit, or in
recognizing a received yellow alarm. In order to transmit the japan yellow alarm the TESFY bit
has to be set.
Transparent Mode Select.
Setting this bit causes unframed data from DSTi channels 0 to 23 and
channel 31 bit 7 to be transmitted transparently onto the DS1 line. Unframed data received from
the DS1 line is piped out on DSTo channels 0 to 23 and channel 31 bit 0.
T1DM Mode Select
. If one, T1 DM Mode is selected. The Ft and Fs pattern is the same as the D4
Mode but a 1011YR0 pattern is sent and detected in Channel 24 of the T1 interface. Bit Y is used
to indicate a yellow Alarm and R bit is used by AT&T for a 8kb/s communication channel.
Extended Super Frame
. Setting this bit enables transmission and reception of the 24 frame
superframe DS1 protocol.
Reserved
. Must be set to 0 for normal operation.
12
JY
(0)
11 TRANSP
(0)
10
T1DM
(0)
9
ESF
(0)
RSV
(0)
CXC
(0)
8
7
Cross Check.
Setting this bit in ESF mode enables a cross check of the CRC-6 remainder before
the frame synchronizer pulls into sync. This process adds at least 6 milliseconds to the frame
synchronization time.
Reframe Select
. These bits set the criteria for an automatic reframe in the event of framing bits
errors. The combinations available are:
RS1 - 0, RS0 - 0 = sliding window of 2 errors out of 4.
RS1 - 0, RS0 - 1 = sliding window of 2 errors out of 5.
RS1 - 1, RS0 - 0 = sliding window of 2 errors out of 6.
RS1 - 1, RS0 - 1 = no reframes due to framing bit errors.
Note that for T1DM mode, the frame boundary starts at the channel 1 data including
synchronization byte (10111YR0) and the following ’S’ bit.
Fs Bit Include
. Only applicable in D4 mode (not ESF). Setting this bit causes errored Fs bits to be
included as framing bit errors. A bad Fs bit will increment the Framing Error Bit Counter, and will
potentially cause a reframe (if it is the second bad framing bit out of 5). The Fs bit of the receive
frame 12 will only be included if D4SECY is set. Setting this bit in D4 (not ESF) mode enables a
check of the Fs bits in addition to the Ft bits during frame synchronization.
Reframe
. Setting this bit causes an automatic reframe.
6
5
RS1
RS0
(00)
4
FSI
(0)
3
REFR
(0)
MFREFR
(0)
2
MultiFrame Reframe
. Only applicable in D4 mode. Setting this bit causes an automatic
multiframe reframe. The signaling bits are frozen until multiframe synchronization is achieved.
Terminal frame synchronization is not affected.
Japan Telecom Synchronization.
If one, the S bit is included in the CRC6 calculation for the
ESF framing Mode.
Transmit Synchronization.
Setting this bit causes the transmit multiframe boundary to be
internally synchronized to the incoming S-bits on DSTi channel 31 bit 0.
Table 78 - T1 Framing Mode Control - R/W Address Y00
1
JTS
(0)
0
TXSYNC
(0)