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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 109/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
109
Bit
Name
Functional Description
15
14
13
PR2
PR1
PR0
(101)
Primary Reference Source.
These three select bits determine the primary reference clock source
for the internal PLL. The clock frequency at the selected reference source must match the PLL
frequency selection.
PR2
PR1
PR0
Primary Reference Source
0
0
0
RXCK[0]
0
0
1
RXCK[1]
0
1
0
RXCK[2]
0
1
1
RXCK[3]
1
0
0
ESYN
1
0
1
CKb
1
1
0
FPb
1
1
1
Reserved
Secondary Reference Source.
These three select bits determine the secondary reference clock
source for the internal PLL. The clock frequency at the selected reference source must match the
PLL frequency selection.
SR2
SR1
SR0
Secondary Reference Source
0
0
0
RXCK[0]
0
0
1
RXCK[1]
0
1
0
RXCK[2]
0
1
1
RXCK[3]
1
0
0
ESYN
1
0
1
CKb
1
1
0
FPb
1
1
1
Reserved
PLL Frequency Selection.
These two select bits determine the input reference clock frequency for
the internal PLL.The clock frequency at the selected reference source must match the PLL
frequency selection.
FS2
FS1
PLL Input Frequency
0
0
Reserved
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
When CKb is selected as a reference source, the clock rate at the CKb pin is divided down to
2.048MHz (CKb/2 in 2Mb/s mode and CKb/8 in 8Mb/s mode). After changing these bits, the PLL
reset bit (Table 70, “T1 & E1 Global Mode Control - R/W Address 900,” on page 106) should be
toggled.
PLL Mode Selection.
These two select bits determine the mode of operation of the internal PLL.
MS2
MS1
PLL Operating Mode
0
0
Normal
0
1
Holdover
1
0
Freerun
1
1
Reserved
When CKb is selected as a reference source, the clock rate at the CKb pin is divided down to
2.048MHz; CKb/2 in 2Mb/s mode and CKb/8 in 8Mb/s mode.
Reference Select.
When low, the primary reference source is used as the timing source to the
PLL. When high, the secondary reference is used as the timing source to the PLL.
TIE Circuit Reset.
When low, the PLL time interval error correction circuit is reset, resulting in a re-
alignment of input phase and output phase.
TIE Circuit Enable.
When high, the PLL time interval error correction circuit is enabled for mode
switches from Primary Holdover to Primary Normal. When low, it is disabled.
Buss Mode.
When zero, the device is in Bus Sync mode, the bi-directional CK and FP pins are
inputs. When one, the device is in PLL Sync mode, the bi-directional CK and FP pins are outputs.
For a detailed description of these modes refer to Section 3.0 Timing.
Table 73 - T1 & E1 Global Timing Control - R/W Address 905
12
11
10
SR2
SR1
SR0
(000)
9
8
FS2
FS1
(11)
7
6
MS2
MS1
(00)
5
RSEL
(0)
TIER
(1)
TIEE
(1)
BUSM
(0)
4
3
2
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