
MT9071
Preliminary Information
116
1
AUTY
(0)
Automatic Y-Bit Operation.
This bit determines the source for the Remote Multiframe Alarm
Indication bit (the Y bit) of the transmit PCM30 signal (time-slot 16 bit 6 of every frame 0 of the
CAS multiframe). If zero, the source for the Y bit is the MSYNC status bit (see Table 105 E1
Synchronization & CRC-4 Remote Status - R Address Y10), and consequently, will change
automatically. That is, Y=0 when multiframe alignment has been acquired (MSYNC=0), and Y=1
when multiframe alignment has not been acquired (MSYNC=1).
If the AUTY bit is set to one, the Y bit is controlled through the Y control bit (see Table 89 - E1 CAS
Control and Data - R/W Address Y05).
Multiframe Reframe.
If one, for at least one frame, and then cleared, the selected framer (Y) will
initiate a search for a new signaling multiframe position. Reframing function is activated on the
one-to-zero transition of the MFRF bit.
Table 79 - E1 Alarms and Framing Control - R/W Address Y00
0
MFRF
(0)
Bit
Name
Functional Description
15-12
11
10
(####)
RZCS1
RZCS0
(00)
Not Used
Receive Zero Code Suppression.
RZCS1
RZCS0
0
0
0
1
1
0
1
1
See Section 4.1.1 T1 Encoding and Decoding Options.
Transmit Zero Code Suppression.
TZCS2
TZCS1
0
0
0
0
0
1
0
1
1
0
1
1
1
X
See Section 4.1.1 T1 Encoding and Decoding Options.
Transmit PDV.
The output of the T1 data to be sent is monitored over a T1 frame and if the
density is less than 12.5%, a bit is added in the non-framing bit.
Transmit Bipolar Eight Zero Substitution.
If one, all zero octets in the transmit path are
substituted with B8ZS codes.
Receive Bipolar Eight Zero Substitution
. If one, B8ZS code words in the receive path are
substituted with all zero octets. Bipolar violations associated with incoming B8ZS words will
not be counted (see Table 120 - T1 Bipolar Violation Counter - R/W Address Y18).
Digital Milliwatt or Digital Test Sequence.
If one, the mu-law digital milliwatt analog test
sequence will be selected by the Per Timeslot Control bits TTSTn and RTSTn (see Table 166 -
T1 Per Channel 1 to 24 Control Registers - R/W Address Y90-YA7). If zero, the PRBS 2
15
-1 bit
error rate test sequence will be selected by control bits TTSTn and RTSTn. The PRBS
generator is reset whenever this bit is set to 1.
Return to zero Non Return to zero.
If one return to zero input and outputs are expected at
the framer-LIU interface. If zero, non return to zero input and output are expected. This is
normally set to zero.
Table 80 - T1 Line Coding Control - R/W Address Y01
Suppression
No Zero Code Suppression
GTE Zero Code Suppression
DDS Zero Code Suppression
Bell Zero Code Suppression
9
8
7
TZCS2
TZCS1
TZCS0
(000)
TZCS0
0
1
0
1
0
X
1
Suppression
No Zero Code Suppression
GTE Zero Code Suppression
DDS Zero Code Suppression
Bell Zero Code Suppression
Jammed Bit 8
Reserved
Reserved
6
TPDV
(0)
TXB8ZS
(0)
RXB8ZS
(0)
5
4
3
ADSEQ
(0)
2
RZNRZ
(0)
Bit
Name
Functional Description