
Preliminary Information
MT9071
161
6
MFSYNI
(0)
Multiframe Synchronization Interrupt.
This bit is one when the corresponding MFSYNL bit in
the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding MFSYNM
bit in the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Framing Bit Error Interrupt.
This bit is one when the corresponding BEIL bit in the T1 Receive
Sync and Alarm Latch - R Address Y24 is set, and the corresponding BEIM bit in the T1 Receive
and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Change of Frame Alignment Interrupt.
This bit is one when the corresponding CFIL bit in the
T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding CFIM bit in the
T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Severely Errored Frame Interrupt.
This bit is one when the corresponding SEFL bit in the T1
Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding SEFM bit in the T1
Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Alarm Indication Signal Interrupt.
This bit is one when the corresponding AISL bit in the T1
Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding AISM bit in the T1
Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
CRC-6 Error Counter Indication Interrupt.
This bit is one when the corresponding CEIL bit in
the T1 Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding CEIM bit in
the T1 Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Digital Loss of Signal Interrupt.
This bit is one when the corresponding LOSL bit in the T1
Receive Sync and Alarm Latch - R Address Y24 is set, and the corresponding LOSM bit in the T1
Receive and Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
Table 149 - T1 Receive and Sync Interrupt Status - R Address Y34
5
BEII
(0)
4
CFII
(0)
3
SEFI
(0)
2
AISI
(0)
1
CEII
0
LOSI
(0)
Bit
Name
Functional Description
15
14
(0)
Not Used
RCRCRI
Remote CRC-4 and RAI Interrupt.
This bit is one when the corresponding RCRCRL bit in the
E1 Sync Latched Status - R Address Y24 is set, and the corresponding RCRCRM bit in the E1
Sync Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
RSLPI
Receive Slip Interrupt.
This bit is one when the corresponding RSLPL bit in the E1 Sync
Latched Status - R Address Y24 is set, and the corresponding RSLPM bit in the E1 Sync
Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
YI
Receive Y-bit Interrupt.
This bit is one when the corresponding YL bit in the E1 Sync Latched
Status - R Address Y24 is set, and the corresponding YM bit in the E1 Sync Interrupt Mask - R/
W Address Y44 is unmasked. This bit is cleared when either this register, or the latched status
register is read.
AUXPI
Auxiliary Pattern Interrupt.
This bit is one when the corresponding AUXPL bit in the E1 Sync
Latched Status - R Address Y24 is set, and the corresponding AUXPM bit in the E1 Sync
Interrupt Mask - R/W Address Y44 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
Table 150 - E1 Sync Interrupt Status - R Address Y34
13
12
11
Bit
Name
Functional Description