- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384760 > MT9071 (Mitel Networks Corporation) Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) PDF資料下載
參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 150/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁當前第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁
MT9071
Preliminary Information
150
6
RCRC0L
Remote CRC-4 and RAI T10 Latch.
When the RCRC0 status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to
one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is
read.
RCRC1L
Remote CRC-4 and RAI T450 Latch.
When the RCRC1 status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to
one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is
read.
CEFSL
Consecutively Errored Frame Alignment Signal Latch.
When the CEFS status bit (E1
Synchronization & CRC-4 Remote Status - R Address Y10) toggles from zero to one, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
RFAILL
Remote CRC-4 Multiframe Generator/Detector Failure Latch.
When the RFAIL status bit
(E1 Synchronization & CRC-4 Remote Status - R Address Y10) toggles from zero to one, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
CSYNCL
Receive CRC-4 Synchronization Latch.
When the CSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
MSYNCL
Receive Multiframe Alignment Latch.
When the MSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
BSYNCL
Receive Basic Frame Alignment Latch.
When the BSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
Table 133 - E1 Sync Latched Status - R Address Y24
5
4
3
2
1
0
Bit
Name
Functional Description
15
D4YL
(0)
D4 Yellow Alarm Latch.
When the D4Y status bit (T1 Synchronization and Alarm Status - R
Address Y10) toggles from zero to one, this status bit is latched to one. It is cleared when either
this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
D4 Yellow Alarm (48 milliseconds) Latch.
When the D4Y48 status bit (T1 Synchronization
and Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It
is cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R
Address Y35 is read.
Secondary D4 Yellow Alarm Latch.
When the SECY status bit (T1 Synchronization and
Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
ESF Yellow Alarm Latch.
When the ESFY status bit (T1 Synchronization and Alarm Status - R
Address Y10) toggles from zero to one, this status bit is latched to one. It is cleared when either
this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
T1DM Yellow Alarm Latched
.When the T1DMY status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from one to zero, this status bit is latched to one. It is cleared
when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is
read.
Not Used
Table 134 - T1 Receive Line Status and Timer Latch - R Address Y25
14
D4Y48L
(0)
13
SECYL
(0)
12
ESFYL
(0)
11
T1DMYL
(0)
10
(0)
Bit
Name
Functional Description
相關PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開關) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開關) |
| MT90826 | Quad Digital Switch(四數(shù)字開關) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級通道開關) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。