
MT9071
Preliminary Information
150
6
RCRC0L
Remote CRC-4 and RAI T10 Latch.
When the RCRC0 status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to
one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is
read.
RCRC1L
Remote CRC-4 and RAI T450 Latch.
When the RCRC1 status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to
one. It is cleared when either this register, or the E1 Sync Interrupt Status - R Address Y34 is
read.
CEFSL
Consecutively Errored Frame Alignment Signal Latch.
When the CEFS status bit (E1
Synchronization & CRC-4 Remote Status - R Address Y10) toggles from zero to one, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
RFAILL
Remote CRC-4 Multiframe Generator/Detector Failure Latch.
When the RFAIL status bit
(E1 Synchronization & CRC-4 Remote Status - R Address Y10) toggles from zero to one, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
CSYNCL
Receive CRC-4 Synchronization Latch.
When the CSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
MSYNCL
Receive Multiframe Alignment Latch.
When the MSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
BSYNCL
Receive Basic Frame Alignment Latch.
When the BSYNC status bit (E1 Synchronization &
CRC-4 Remote Status - R Address Y10) toggles from zero to one, or from one to zero, this
status bit is latched to one. It is cleared when either this register, or the E1 Sync Interrupt
Status - R Address Y34 is read.
Table 133 - E1 Sync Latched Status - R Address Y24
5
4
3
2
1
0
Bit
Name
Functional Description
15
D4YL
(0)
D4 Yellow Alarm Latch.
When the D4Y status bit (T1 Synchronization and Alarm Status - R
Address Y10) toggles from zero to one, this status bit is latched to one. It is cleared when either
this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
D4 Yellow Alarm (48 milliseconds) Latch.
When the D4Y48 status bit (T1 Synchronization
and Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It
is cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R
Address Y35 is read.
Secondary D4 Yellow Alarm Latch.
When the SECY status bit (T1 Synchronization and
Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
ESF Yellow Alarm Latch.
When the ESFY status bit (T1 Synchronization and Alarm Status - R
Address Y10) toggles from zero to one, this status bit is latched to one. It is cleared when either
this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
T1DM Yellow Alarm Latched
.When the T1DMY status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from one to zero, this status bit is latched to one. It is cleared
when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is
read.
Not Used
Table 134 - T1 Receive Line Status and Timer Latch - R Address Y25
14
D4Y48L
(0)
13
SECYL
(0)
12
ESFYL
(0)
11
T1DMYL
(0)
10
(0)
Bit
Name
Functional Description