
MT9071
Preliminary Information
20
5.0
E1 Interface and Framing .............................................................................................42
5.1
E1 Interface Overview............................................................................................................................42
5.1.1
E1 Encoding and Decoding Options............................................................................................... 43
5.2
E1 Frame Alignment...............................................................................................................................43
5.3
E1 Reframe............................................................................................................................................44
5.4
E1 Multiframing ......................................................................................................................................44
5.4.1
E1 CAS Multiframing...................................................................................................................... 44
5.4.2
E1 CRC-4 Multiframing................................................................................................................... 44
5.4.3
E1 Automatic CRC-4 Interworking.................................................................................................. 45
5.5
E1 Framing Algorithms...........................................................................................................................47
6.0
Slip Buffers and Jitter Attenuators..............................................................................49
6.1
T1 Slip Buffer..........................................................................................................................................49
6.1.1
T1 Transmit Slip Buffer................................................................................................................... 49
6.1.2
T1 Receive Slip Buffer.................................................................................................................... 50
6.1.3
T1 Receive Elastic Buffer Bypass .................................................................................................. 51
6.2
E1 Slip Buffer .........................................................................................................................................52
6.2.1
E1 Receive Slip Buffer.................................................................................................................... 52
6.2.2
E1 Receive Slip Buffer Bypass....................................................................................................... 53
6.3
E1 Transmit Jitter Attenuator..................................................................................................................53
7.0
MT9071 Access and Control.........................................................................................54
7.1
7.2
Quad Transceiver Organization .............................................................................................................54
Processor Interface (A11-A0, D15-D0, IM, DS, R/W, CS, IRQ, Pins)....................................................54
7.2.1
Transceiver and Register Access................................................................................................... 54
7.2.2
MT9071 Identification Code............................................................................................................ 55
7.2.3
CS and IRQ.................................................................................................................................... 55
7.3
ST-BUS Interface (DSTo, DSTo, CSTi, CSTo Pins)..............................................................................55
7.3.1
ST-BUS 2.048Mb/s and 8.192Mb/s Mapping................................................................................. 55
7.4
Data Link Interface (RxD and RxCK Pins) .............................................................................................55
7.5
CRC-4 and CAS Multiframe Boundary (TxMF Pins)..............................................................................55
7.6
Reset Operation (RESET, TRST Pins) ..................................................................................................56
7.7
Control Pins............................................................................................................................................56
7.7.1
Transmit AIS Operation (TAIS Pin) ................................................................................................ 56
7.7.2
IEEE 1149.1-1990 Test Access Port (TAP).................................................................................... 56
8.0
JTAG Operation .............................................................................................................57
8.1
8.2
8.3
8.4
Test Access Port (TAP)..........................................................................................................................57
Test Access Port (TAP) Controller.........................................................................................................58
Instruction Register ................................................................................................................................58
Test Data Registers................................................................................................................................58
8.4.1
Identification Register..................................................................................................................... 58
8.4.2
The Bypass Register...................................................................................................................... 59