
Preliminary Information
MT9071
29
3.1.1
Bus Synchronization Mode
Bus Synchronization is typically used when a slave clock source, synchronized to the backplane bus is
required.
In Bus Synchronization Mode, the MT9071 uses an internal PLL to provide jitter free timing which is
synchronized to the clock or frame pulse signals which are externally applied to the CKb and FPb pins. Only
the transmit clock uses the internal jitter free timing. Consequently, when in E1 Mode, the jitter attenuator
should be enabled to ensure the data sent to the transmitter is in sync with the jitter free transmit clock. The
accuracy of the transmit timing is equal to the accuracy of the clock at the CKb/FPb pin.
For circuit details, refer to Figure 4 - T1 & E1 Bus Sync Mode.
Figure 1 -
Figure 2 -
Figure 3 -
Timing Mode
Register and Bits
Source for MT9071 Timing
Enable Jitter
Attenuator For:
T1 & E1 Global
Timing Control - R/W
Address 905
MS2 MS1 BUSM
ESYNI
Bus Sync
000X
CKb pin or FPb pin (these are in input mode CKi, FPi) E1 Always & T1/
E1 RLBK
T1/E1 RLBK Only
T1/E1 RLBK Only
Free-Run
Line Sync
101X
001X
OSCi input pin
One of 4 receive clock signals at the RXCK[n] pins
(extracted from RTIP[n] and RRNG[n])
ESYN pin
This mode is only applicable during Line Sync Mode
or External Sync Mode after the source timing is
corrupted. Timing is based on a combination of the
OSCi input pin and either one of the receive line
signals at the RTIP[n] and RRNG[n] pins or the ESYN
pin
This mode is only applicable following Line Sync Mode
or External Sync Mode. Timing is based on a
combination of the OSCi input pin and either one of
the receive line signals at the RTIP[n] and RRNG[n]
pins or the ESYN pin
External Sync
Auto-Holdover
0010
001X
T1/E1 RLBK Only
T1/E1 RLBK Only
Holdover
011X
T1/E1 RLBK Only
Notes:
1. The transmit jitter is always attenuated by the timing signal from the internal PLL, consequently, the timing mode does not affect
the intrinsic transmit jitter.
2. The backplane jitter (i.e. CSTo and DSTo) is attenuated for all modes except Bus Sync Mode where the jitter from the CKb and FPb
pins is passed to the backplane circuitry unfiltered.
3. When in E1 mode and Bus Sync Mode, the jitter attenuator must be enabled. This guarantees that the jitter free transmit clock is in
phase with the transmit data which may be jittered.
Table 1 - E1 and T1 Timing Modes Summary