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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 148/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
148
Bit
Name
Functional Description
15
BEOL
(0)
Framing Bit Error Counter Overflow Latch.
When the corresponding counter (T1 Framing
Bit Error Counter - R/W Address Y17) overflows to 0, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive and Sync Interrupt Status - R Address
Y34 is read.
CRC-6 Error Counter Overflow Latch.
When the corresponding counter (T1 CRC-6 Error
Counter - R/W Address Y19) overflows to 0, this status bit is latched to one. It is cleared
when either this register, or the T1 Receive and Sync Interrupt Status - R Address Y34 is
read.
Out Of Frame Counter Overflow Latch.
When the corresponding counter (T1 Out of
Frame and Change of Frame Counters - R/W Address Y1A) overflows (to 0), this status bit
is latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
Change of Frame Alignment Counter Overflow Latch.
When the corresponding counter
(T1 Out of Frame and Change of Frame Counters - R/W Address Y1A) overflows to 0, this
status bit is latched to one. It is cleared when either this register, or the T1 Receive and
Sync Interrupt Status - R Address Y34 is read.
Bipolar Violation Counter Overflow Latch.
When the corresponding counter (T1 Bipolar
Violation Counter - R/W Address Y18) overflows to 0, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive and Sync Interrupt Status - R Address
Y34 is read.
PRBS Error Counter Overflow Latch.
When the corresponding counter (T1 PRBS CRC
Multiframe and PRBS Error Counter - R/W Address Y15) overflows to 0, this status bit is
latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
PRBS CRC-6 Multiframe Counter Overflow Latch.
When the corresponding counter (T1
PRBS CRC Multiframe and PRBS Error Counter - R/W Address Y15) overflows to 0, this
status bit is latched to one. It is cleared when either this register, or the T1 Receive and
Sync Interrupt Status - R Address Y34 is read.
Multiframe Out of Frame Counter Overflow Latch.
When the corresponding counter (T1
Multiframe Out of Frame Counter - R/W Address Y16) overflows to 0, this status bit is
latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
Terminal Out Of Sync Latch.
When the TFSYNC status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from zero to one, or from one to zero, this status bit is
latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
Multiframes Out Of Sync Latch.
When the MFSYNC status bit (T1 Synchronization and
Alarm Status - R Address Y10) toggles from zero to one, or from one to zero, this status bit
is latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
Framing Bit Error Counter Indication Latch.
When the corresponding counter (T1
Framing Bit Error Counter - R/W Address Y17) is incremented by one, this status bit is
latched to one. It is cleared when either this register, or the T1 Receive and Sync Interrupt
Status - R Address Y34 is read.
Change of Frame Counter Indication Latch.
When the corresponding counter (T1 Out of
Frame and Change of Frame Counters - R/W Address Y1A) is incremented by one, this
status bit is latched to one. It is cleared when either this register, or the T1 Receive and
Sync Interrupt Status - R Address Y34 is read.
Table 132 - T1 Receive Sync and Alarm Latch - R Address Y24
14
CEOL
(0)
13
OFOL
(0)
12
CFOL
(0)
11
VEOL
(0)
10
PEOL
(0)
9
PCOL
(0)
8
MFOL
(0)
7
TFSYNL
(0)
6
MFSYNL
(0)
5
BEIL
(0)
4
CFIL
(0)
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