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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 131/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
131
Bit
Name
Functional Description
15-14
13
(##)
Not Used
Terminal Frame Synchronization
. Indicates the Terminal Frame Synchronization status (1 -
loss; 0 - acquired). For ESF links, terminal frame synchronization and multiframe
synchronization are synonymous. This bit is also used for indicating T1DM sync status.
Multiframe Synchronization.
Indicates the Multiframe Synchronization status (1 - loss; 0 -
acquired). For ESF links multiframe synchronization and terminal frame synchronization are
synonymous.
Severely Errored Frame
. This bit toggles when 2 of the last 6 received framing bits are in error.
The framing bits monitored are the ESF framing bits for ESF links and the Ft and Fs bits for D4
links (see Table 78 - T1 Framing Mode Control - R/W Address Y00).
Digital Loss of Signal.
This bit goes high after the detection of 192 or 32 consecutive zeros as
set by the control bit L32Z detailed in Table 84 - T1 Transmit Error Control - R/W Address Y03. It
returns low when the incoming pulse density exceeds 12.5% over a 250 microsecond period.
D4 Yellow Alarm.
This bit is set if bit position 2 of virtually every DS0 channel is a zero for a
period of 600 milliseconds. The alarm is tolerant of errors by permitting up to 16 ones in a 48
millisecond integration period. The alarm clears in 200 milliseconds after being removed from
the line.
D4 Yellow Alarm - 48 millisecond sample.
This bit is set if bit position 2 of virtually every DS0
channel is a zero for a period of 48 milliseconds. The alarm is tolerant of errors by permitting up
to 16 ones in the integration period. This bit is updated every 48 milliseconds.
Secondary D4 Yellow Alarm.
This bit is set if 2 consecutive ’1’s are received in the S-bit
position of the 12th frame of the D4 superframe.
ESF Yellow Alarm.
This bit is set if the ESF yellow alarm (8 zero’s followed by 8 one’s) is
received in seven or more codewords out of ten in the Bit Oriented Message location which are
the FDL bits.
AIS Alarm.
This bit is set if less than 5 zeros are received in a 3 millisecond window. This bit is
high after power up.
Pulse Density Violation.
This bit toggles if the receive data fails to meet ones density
requirements. It will toggle upon detection of 16 consecutive zeros on the line data, or if there
are less than N ones in a window of 8(N+1) bits - where N = 1 to 23.
Line Loopback Enable Detect.
This bit is set when a framed or unframed repeating pattern
(default pattern is 00001) has been detected during a 48 millisecond interval. Up to fifteen errors
are permitted per integration period. The code detected is dependent on the RXLACM7-0 data
bits detailed in Table 103 - T1 Receive Loop Activate Code Match Control - R/W Address Y0F.
Line Loopback Disable Detect.
This bit is set when a framed or unframed repeating pattern
(default pattern is 001) has been detected during a 48 millisecond interval. Up to fifteen errors
are permitted per integration period.The code detected is dependent on the RXLACM7-0 data
bits detailed in Table 177 - T1 Receive Loop Deactivate Code Match - R/W Address YF0.
T1DM Received R bit
. If T1DM mode is selected, this bit indicates the status of the bit (R-bit)
received on the DS1 link in bit position 1 of timeslot 24 of all frames. This bit is used for an AT&T
8 Kb/s communications channel. Updated on a frame basis.
T1DM Received Yellow Alarm
. If T1DM mode is selected, this bit indicates the status of the bit
(Y-bit) received on the DS1 link in bit position 2 of timeslot 24 of all frames. If zero, there is
currently a yellow alarm condition. Updated on a frame basis.
Table 104 - T1 Synchronization and Alarm Status - R Address Y10
TFSYNC
(0)
12
MFSYNC
(0)
11
SEF
(0)
10
LOS
(0)
9
D4Y
(0)
8
D4Y48
(0)
7
SECY
(0)
ESFY
(0)
6
5
AIS
(0)
PDV
(0)
4
3
LLED
(0)
2
LLDD
(0)
1
T1DMR
(0)
0
T1DMY
(1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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